Commit f02b5337 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration 



The CSI1 PHY reference clock is limited to 125 MHz according to:
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
Table 5-1. Clock Root Table (continued) / page 307
Slice Index n = 123 .

Currently the IMX8MM_CLK_CSI1_PHY_REF clock is configured to be
fed directly from 1 GHz PLL2 , which overclocks them. Instead, drop
the configuration altogether, which defaults the clock to 24 MHz REF
clock input, which for the PHY reference clock is just fine.

Based on a patch from Marek Vasut for the imx8mn.

Fixes: e523b7c5 ("arm64: dts: imx8mm: Add CSI nodes")
Signed-off-by: default avatarFabio Estevam <festevam@denx.de>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Reviewed-by: default avatarAdam Ford <aford173@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 926c7335

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+3 −4
Original line number Diff line number Diff line
@@ -1221,10 +1221,9 @@ 
				compatible = "fsl,imx8mm-mipi-csi2";

				reg = <0x32e30000 0x1000>;

				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,

						  <&clk IMX8MM_CLK_CSI1_PHY_REF>;

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,

							  <&clk IMX8MM_SYS_PLL2_1000M>;

				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;



				clock-frequency = <333000000>;

				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,

					 <&clk IMX8MM_CLK_CSI1_ROOT>,