Commit efe80a28 authored by Alex Deucher's avatar Alex Deucher Committed by Wen Zhiwei
Browse files

drm/amdgpu/hdp4.0: do a posting read when flushing HDP 

stable inclusion
from stable-v6.6.69
commit f60770d660dc6e1e371c7826ad4224143eb51551
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBNEPJ

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f60770d660dc6e1e371c7826ad4224143eb51551



--------------------------------

[ Upstream commit c9b8dcabb52afe88413ff135a0953e3cc4128483 ]

Need to read back to make sure the write goes through.

Cc: David Belanger <david.belanger@amd.com>
Reviewed-by: default avatarFrank Min <frank.min@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent b0f17c62

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

+8 −4
Original line number Diff line number Diff line
@@ -40,11 +40,13 @@ 
static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg)

	if (!ring || !ring->funcs->emit_wreg) {

		WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	else

		RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);

	} else {

		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	}

}



static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,

				    struct amdgpu_ring *ring)
@@ -53,12 +55,14 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, 
	    adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 2))

		return;



	if (!ring || !ring->funcs->emit_wreg)

	if (!ring || !ring->funcs->emit_wreg) {

		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);

	else

		RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);

	} else {

		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(

			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);

	}

}



static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,

					   void *ras_error_status)