Commit efd6d85a authored by Boyuan Zhang's avatar Boyuan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/vcn3.0: remove old DPG workaround 



Port from VCN2.5
SCRATCH2 is used to keep decode wptr as a workaround
which fix a hardware DPG decode wptr update bug for
vcn2.5 beforehand.

Signed-off-by: default avatarBoyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.9.x
parent ac2db948

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+0 −7
Original line number Diff line number Diff line
@@ -1587,9 +1587,6 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 
				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));



				WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,

					RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);



				/* Unstall DPG */

				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

					0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1650,10 +1647,6 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;



	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)

		WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,

			lower_32_bits(ring->wptr) | 0x80000000);



	if (ring->use_doorbell) {

		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);

		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));