Loading arch/arm/mach-at91/cpuidle.c +7 −1 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ #include <linux/export.h> #include <asm/proc-fns.h> #include <asm/cpuidle.h> #include <mach/cpu.h> #include "pm.h" Loading @@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { at91_standby(); if (cpu_is_at91rm9200()) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); else at91sam9_standby(); return index; } Loading arch/arm/mach-at91/pm.c +8 −4 Original line number Diff line number Diff line Loading @@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ at91_standby(); if (cpu_is_at91rm9200()) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); else at91sam9_standby(); break; case PM_SUSPEND_ON: Loading Loading @@ -307,10 +312,9 @@ static int __init at91_pm_init(void) pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); #ifdef CONFIG_ARCH_AT91RM9200 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ if (cpu_is_at91rm9200()) at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); #endif suspend_set_ops(&at91_pm_ops); Loading arch/arm/mach-at91/pm.h +0 −13 Original line number Diff line number Diff line Loading @@ -12,7 +12,6 @@ #define __ARCH_ARM_MACH_AT91_PM #include <mach/at91_ramc.h> #ifdef CONFIG_ARCH_AT91RM9200 #include <mach/at91rm9200_sdramc.h> /* Loading Loading @@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void) "r" (lpr)); } #define at91_standby at91rm9200_standby #elif defined(CONFIG_ARCH_AT91SAM9G45) /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ Loading Loading @@ -75,10 +70,6 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } #define at91_standby at91sam9g45_standby #else #ifdef CONFIG_ARCH_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; Loading @@ -102,8 +93,4 @@ static inline void at91sam9_standby(void) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); } #define at91_standby at91sam9_standby #endif #endif Loading
arch/arm/mach-at91/cpuidle.c +7 −1 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ #include <linux/export.h> #include <asm/proc-fns.h> #include <asm/cpuidle.h> #include <mach/cpu.h> #include "pm.h" Loading @@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { at91_standby(); if (cpu_is_at91rm9200()) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); else at91sam9_standby(); return index; } Loading
arch/arm/mach-at91/pm.c +8 −4 Original line number Diff line number Diff line Loading @@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ at91_standby(); if (cpu_is_at91rm9200()) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); else at91sam9_standby(); break; case PM_SUSPEND_ON: Loading Loading @@ -307,10 +312,9 @@ static int __init at91_pm_init(void) pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); #ifdef CONFIG_ARCH_AT91RM9200 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ if (cpu_is_at91rm9200()) at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); #endif suspend_set_ops(&at91_pm_ops); Loading
arch/arm/mach-at91/pm.h +0 −13 Original line number Diff line number Diff line Loading @@ -12,7 +12,6 @@ #define __ARCH_ARM_MACH_AT91_PM #include <mach/at91_ramc.h> #ifdef CONFIG_ARCH_AT91RM9200 #include <mach/at91rm9200_sdramc.h> /* Loading Loading @@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void) "r" (lpr)); } #define at91_standby at91rm9200_standby #elif defined(CONFIG_ARCH_AT91SAM9G45) /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ Loading Loading @@ -75,10 +70,6 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } #define at91_standby at91sam9g45_standby #else #ifdef CONFIG_ARCH_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; Loading @@ -102,8 +93,4 @@ static inline void at91sam9_standby(void) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); } #define at91_standby at91sam9_standby #endif #endif