Commit efd01cd3 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915: Drop has_ddi from device info



No need to have this parameter in intel_device_info struct
as all platforms with display version 9 or newer, haswell or broadwell
supports it.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505193524.276400-5-jose.souza@intel.com
parent b6411373
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+3 −1
Original line number Original line Diff line number Diff line
@@ -1293,7 +1293,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))
#define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))


#define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
#define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_DDI(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9 || \
					  IS_BROADWELL(dev_priv) || \
					  IS_HASWELL(dev_priv))
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
#define HAS_PSR_HW_TRACKING(dev_priv) \
#define HAS_PSR_HW_TRACKING(dev_priv) \
+0 −3
Original line number Original line Diff line number Diff line
@@ -535,7 +535,6 @@ static const struct intel_device_info vlv_info = {
	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
	.display.has_ddi = 1, \
	.display.has_fpga_dbg = 1, \
	.display.has_fpga_dbg = 1, \
	.display.has_dp_mst = 1, \
	.display.has_dp_mst = 1, \
	.has_rc6p = 0 /* RC6p removed-by HSW */, \
	.has_rc6p = 0 /* RC6p removed-by HSW */, \
@@ -683,7 +682,6 @@ static const struct intel_device_info skl_gt4_info = {
		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
	.has_64bit_reloc = 1, \
	.has_64bit_reloc = 1, \
	.display.has_ddi = 1, \
	.display.has_fpga_dbg = 1, \
	.display.has_fpga_dbg = 1, \
	.display.fbc_mask = BIT(INTEL_FBC_A), \
	.display.fbc_mask = BIT(INTEL_FBC_A), \
	.display.has_hdcp = 1, \
	.display.has_hdcp = 1, \
@@ -932,7 +930,6 @@ static const struct intel_device_info adl_s_info = {
	.dbuf.size = 4096,							\
	.dbuf.size = 4096,							\
	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
		BIT(DBUF_S4),							\
		BIT(DBUF_S4),							\
	.display.has_ddi = 1,							\
	.display.has_dmc = 1,							\
	.display.has_dmc = 1,							\
	.display.has_dp_mst = 1,						\
	.display.has_dp_mst = 1,						\
	.display.has_dsb = 1,							\
	.display.has_dsb = 1,							\
+0 −1
Original line number Original line Diff line number Diff line
@@ -162,7 +162,6 @@ enum intel_ppgtt_type {
	func(cursor_needs_physical); \
	func(cursor_needs_physical); \
	func(has_cdclk_crawl); \
	func(has_cdclk_crawl); \
	func(has_dmc); \
	func(has_dmc); \
	func(has_ddi); \
	func(has_dp_mst); \
	func(has_dp_mst); \
	func(has_dsb); \
	func(has_dsb); \
	func(has_dsc); \
	func(has_dsc); \