Commit ef8281ab authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio
Browse files

drm/i915/mtl: add GSC CS reset support 



The GSC CS has its own dedicated bit in the GDRST register.

Bspec: 52549
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221102171047.2787951-5-daniele.ceraolospurio@intel.com
parent c07ee636

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −0
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id) 
			[CCS1]  = GEN11_GRDOM_RENDER,

			[CCS2]  = GEN11_GRDOM_RENDER,

			[CCS3]  = GEN11_GRDOM_RENDER,

			[GSC0]  = GEN12_GRDOM_GSC,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -643,6 +643,7 @@ 
#define   XEHPC_GRDOM_BLT3			REG_BIT(26)

#define   XEHPC_GRDOM_BLT2			REG_BIT(25)

#define   XEHPC_GRDOM_BLT1			REG_BIT(24)

#define   GEN12_GRDOM_GSC			REG_BIT(21)

#define   GEN11_GRDOM_SFC3			REG_BIT(20)

#define   GEN11_GRDOM_SFC2			REG_BIT(19)

#define   GEN11_GRDOM_SFC1			REG_BIT(18)