Commit ef80c95c authored by David Virag's avatar David Virag Committed by Krzysztof Kozlowski
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clk: samsung: exynos7885: Correct "div4" clock parents 



"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.

Fixes: 45bd8166 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: default avatarDavid Virag <virag.david003@gmail.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20221013151341.151208-1-virag.david003@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 9abf2313

drivers/clk/samsung/clk-exynos7885.c

+2 −2
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { 
	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),

	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",

	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),

	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",

	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",

	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),

	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",

	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
@@ -239,7 +239,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { 
	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),

	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",

	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),

	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",

	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",

	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),



	/* CORE */