Commit ef4ed780 authored by Richard Weinberger's avatar Richard Weinberger
Browse files

Merge tag 'nand/for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next 

MTD core:
* Handle possible -EPROBE_DEFER from parse_mtd_partitions()

NAND core:
* Fix error handling in nand_prog_page_op() (x2)
* Add a helper to retrieve the number of ECC bytes per step
* Add a helper to retrieve the number of ECC steps
* Let ECC engines advertize the exact number of steps
* ECC Hamming:
  - Populate the public nsteps field
  - Use the public nsteps field
* ECC BCH:
  - Populate the public nsteps field
  - Use the public nsteps field

Raw NAND core:
* Add support for secure regions in NAND memory
* Try not to use the ECC private structures
* Remove duplicate include in rawnand.h
* BBT:
  - Skip bad blocks when searching for the BBT in NAND

Raw NAND controller drivers:
* Qcom:
  - Convert bindings to YAML
  - Use dma_mapping_error() for error check
  - Add missing nand_cleanup() in error path
  - Return actual error code instead of -ENODEV
  - Update last code word register
  - Add helper to configure location register
  - Rename parameter name in macro
  - Add helper to check last code word
  - Convert nandc to chip in Read/Write helper
  - Update register macro name for 0x2c offset
* GPMI:
  - Fix a double free in gpmi_nand_init
* Rockchip:
  - Use flexible-array member instead of zero-length array
* Atmel:
  - Update ecc_stats.corrected counter
* MXC:
  - Remove unneeded of_match_ptr()
* R852:
  - replace spin_lock_irqsave by spin_lock in hard IRQ
* Brcmnand:
  - Move to polling in pio mode on oops write
  - Read/write oob during EDU transfer
  - Fix OOB R/W with Hamming ECC
* FSMC:
  - Fix error code in fsmc_nand_probe()
* OMAP:
  - Use ECC information from the generic structures

SPI-NAND core:
* Add missing MODULE_DEVICE_TABLE()

SPI-NAND drivers:
* gigadevice: Support GD5F1GQ5UExxG
parents 256437eb 32cbc7cb

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+7 −0
Original line number Diff line number Diff line
@@ -143,6 +143,13 @@ patternProperties: 
          Ready/Busy pins. Active state refers to the NAND ready state and

          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.



      secure-regions:

        $ref: /schemas/types.yaml#/definitions/uint64-matrix

        description:

          Regions in the NAND chip which are protected using a secure element

          like Trustzone. This property contains the start address and size of

          the secure regions present.



    required:

      - reg

Documentation/devicetree/bindings/mtd/qcom,nandc.yaml

0 → 100644
+196 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm NAND controller



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



properties:

  compatible:

    enum:

      - qcom,ipq806x-nand

      - qcom,ipq4019-nand

      - qcom,ipq6018-nand

      - qcom,ipq8074-nand

      - qcom,sdx55-nand



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Core Clock

      - description: Always ON Clock



  clock-names:

    items:

      - const: core

      - const: aon



  "#address-cells": true

  "#size-cells": true



patternProperties:

  "^nand@[a-f0-9]$":

    type: object

    properties:

      nand-bus-width:

        const: 8



      nand-ecc-strength:

        enum: [1, 4, 8]



      nand-ecc-step-size:

        enum:

          - 512



allOf:

  - $ref: "nand-controller.yaml#"



  - if:

      properties:

        compatible:

          contains:

            const: qcom,ipq806x-nand

    then:

      properties:

        dmas:

          items:

            - description: rxtx DMA channel



        dma-names:

          items:

            - const: rxtx



        qcom,cmd-crci:

          $ref: /schemas/types.yaml#/definitions/uint32

          description:

            Must contain the ADM command type CRCI block instance number

            specified for the NAND controller on the given platform



        qcom,data-crci:

          $ref: /schemas/types.yaml#/definitions/uint32

          description:

            Must contain the ADM data type CRCI block instance number

            specified for the NAND controller on the given platform



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,ipq4019-nand

              - qcom,ipq6018-nand

              - qcom,ipq8074-nand

              - qcom,sdx55-nand



    then:

      properties:

        dmas:

          items:

            - description: tx DMA channel

            - description: rx DMA channel

            - description: cmd DMA channel



        dma-names:

          items:

            - const: tx

            - const: rx

            - const: cmd



required:

  - compatible

  - reg

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>

    nand-controller@1ac00000 {

      compatible = "qcom,ipq806x-nand";

      reg = <0x1ac00000 0x800>;



      clocks = <&gcc EBI2_CLK>,

               <&gcc EBI2_AON_CLK>;

      clock-names = "core", "aon";



      dmas = <&adm_dma 3>;

      dma-names = "rxtx";

      qcom,cmd-crci = <15>;

      qcom,data-crci = <3>;



      #address-cells = <1>;

      #size-cells = <0>;



      nand@0 {

        reg = <0>;



        nand-ecc-strength = <4>;

        nand-bus-width = <8>;



        partitions {

          compatible = "fixed-partitions";

          #address-cells = <1>;

          #size-cells = <1>;



          partition@0 {

            label = "boot-nand";

            reg = <0 0x58a0000>;

          };



          partition@58a0000 {

            label = "fs-nand";

            reg = <0x58a0000 0x4000000>;

          };

        };

      };

    };



    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>

    nand-controller@79b0000 {

      compatible = "qcom,ipq4019-nand";

      reg = <0x79b0000 0x1000>;



      clocks = <&gcc GCC_QPIC_CLK>,

               <&gcc GCC_QPIC_AHB_CLK>;

      clock-names = "core", "aon";



      dmas = <&qpicbam 0>,

             <&qpicbam 1>,

             <&qpicbam 2>;

      dma-names = "tx", "rx", "cmd";



      #address-cells = <1>;

      #size-cells = <0>;



      nand@0 {

        reg = <0>;

        nand-ecc-strength = <4>;

        nand-bus-width = <8>;



        partitions {

          compatible = "fixed-partitions";

          #address-cells = <1>;

          #size-cells = <1>;



          partition@0 {

            label = "boot-nand";

            reg = <0 0x58a0000>;

          };



          partition@58a0000 {

            label = "fs-nand";

            reg = <0x58a0000 0x4000000>;

          };

        };

      };

    };



...

Documentation/devicetree/bindings/mtd/qcom_nandc.txt

deleted100644 → 0
+0 −142
Original line number Diff line number Diff line 
* Qualcomm NAND controller



Required properties:

- compatible:		must be one of the following:

    * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x

			    SoC and it uses ADM DMA

    * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in

                            IPQ4019 SoC and it uses BAM DMA

    * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in

                            IPQ6018 SoC and it uses BAM DMA

    * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in

                            IPQ8074 SoC and it uses BAM DMA

    * "qcom,sdx55-nand"   - for QPIC NAND controller v2.0.0 being used in

                            SDX55 SoC and it uses BAM DMA



- reg:			MMIO address range

- clocks:		must contain core clock and always on clock

- clock-names:		must contain "core" for the core clock and "aon" for the

			always on clock



EBI2 specific properties:

- dmas:			DMA specifier, consisting of a phandle to the ADM DMA

			controller node and the channel number to be used for

			NAND. Refer to dma.txt and qcom_adm.txt for more details

- dma-names:		must be "rxtx"

- qcom,cmd-crci:	must contain the ADM command type CRCI block instance

			number specified for the NAND controller on the given

			platform

- qcom,data-crci:	must contain the ADM data type CRCI block instance

			number specified for the NAND controller on the given

			platform



QPIC specific properties:

- dmas:			DMA specifier, consisting of a phandle to the BAM DMA

			and the channel number to be used for NAND. Refer to

			dma.txt, qcom_bam_dma.txt for more details

- dma-names:		must contain all 3 channel names : "tx", "rx", "cmd"

- #address-cells:	<1> - subnodes give the chip-select number

- #size-cells:		<0>



* NAND chip-select



Each controller may contain one or more subnodes to represent enabled

chip-selects which (may) contain NAND flash chips. Their properties are as

follows.



Required properties:

- reg:			a single integer representing the chip-select

			number (e.g., 0, 1, 2, etc.)

- #address-cells:	see partition.txt

- #size-cells:		see partition.txt



Optional properties:

- nand-bus-width:	see nand-controller.yaml

- nand-ecc-strength:	see nand-controller.yaml. If not specified, then ECC strength will

			be used according to chip requirement and available

			OOB size.



Each nandcs device node may optionally contain a 'partitions' sub-node, which

further contains sub-nodes describing the flash partition mapping. See

partition.txt for more detail.



Example:



nand-controller@1ac00000 {

	compatible = "qcom,ipq806x-nand";

	reg = <0x1ac00000 0x800>;



	clocks = <&gcc EBI2_CLK>,

		 <&gcc EBI2_AON_CLK>;

	clock-names = "core", "aon";



	dmas = <&adm_dma 3>;

	dma-names = "rxtx";

	qcom,cmd-crci = <15>;

	qcom,data-crci = <3>;



	#address-cells = <1>;

	#size-cells = <0>;



	nand@0 {

		reg = <0>;



		nand-ecc-strength = <4>;

		nand-bus-width = <8>;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			partition@0 {

				label = "boot-nand";

				reg = <0 0x58a0000>;

			};



			partition@58a0000 {

				label = "fs-nand";

				reg = <0x58a0000 0x4000000>;

			};

		};

	};

};



nand-controller@79b0000 {

	compatible = "qcom,ipq4019-nand";

	reg = <0x79b0000 0x1000>;



	clocks = <&gcc GCC_QPIC_CLK>,

		<&gcc GCC_QPIC_AHB_CLK>;

	clock-names = "core", "aon";



	dmas = <&qpicbam 0>,

		<&qpicbam 1>,

		<&qpicbam 2>;

	dma-names = "tx", "rx", "cmd";



	#address-cells = <1>;

	#size-cells = <0>;



	nand@0 {

		reg = <0>;

		nand-ecc-strength = <4>;

		nand-bus-width = <8>;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			partition@0 {

				label = "boot-nand";

				reg = <0 0x58a0000>;

			};



			partition@58a0000 {

				label = "fs-nand";

				reg = <0x58a0000 0x4000000>;

			};

		};

	};

};

drivers/mtd/mtdcore.c

+3 −0
Original line number Diff line number Diff line
@@ -822,6 +822,9 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types, 


	/* Prefer parsed partitions over driver-provided fallback */

	ret = parse_mtd_partitions(mtd, types, parser_data);

	if (ret == -EPROBE_DEFER)

		goto out;



	if (ret > 0)

		ret = 0;

	else if (nr_parts)

drivers/mtd/nand/ecc-sw-bch.c

+5 −5
Original line number Diff line number Diff line
@@ -236,7 +236,6 @@ int nand_ecc_sw_bch_init_ctx(struct nand_device *nand) 
		goto free_engine_conf;



	engine_conf->code_size = code_size;

	engine_conf->nsteps = nsteps;

	engine_conf->calc_buf = kzalloc(mtd->oobsize, GFP_KERNEL);

	engine_conf->code_buf = kzalloc(mtd->oobsize, GFP_KERNEL);

	if (!engine_conf->calc_buf || !engine_conf->code_buf) {
@@ -245,6 +244,7 @@ int nand_ecc_sw_bch_init_ctx(struct nand_device *nand) 
	}



	nand->ecc.ctx.priv = engine_conf;

	nand->ecc.ctx.nsteps = nsteps;

	nand->ecc.ctx.total = nsteps * code_size;



	ret = nand_ecc_sw_bch_init(nand);
@@ -253,7 +253,7 @@ int nand_ecc_sw_bch_init_ctx(struct nand_device *nand) 


	/* Verify the layout validity */

	if (mtd_ooblayout_count_eccbytes(mtd) !=

	    engine_conf->nsteps * engine_conf->code_size) {

	    nand->ecc.ctx.nsteps * engine_conf->code_size) {

		pr_err("Invalid ECC layout\n");

		ret = -EINVAL;

		goto cleanup_bch_ctx;
@@ -295,7 +295,7 @@ static int nand_ecc_sw_bch_prepare_io_req(struct nand_device *nand, 
	struct mtd_info *mtd = nanddev_to_mtd(nand);

	int eccsize = nand->ecc.ctx.conf.step_size;

	int eccbytes = engine_conf->code_size;

	int eccsteps = engine_conf->nsteps;

	int eccsteps = nand->ecc.ctx.nsteps;

	int total = nand->ecc.ctx.total;

	u8 *ecccalc = engine_conf->calc_buf;

	const u8 *data;
@@ -333,7 +333,7 @@ static int nand_ecc_sw_bch_finish_io_req(struct nand_device *nand, 
	int eccsize = nand->ecc.ctx.conf.step_size;

	int total = nand->ecc.ctx.total;

	int eccbytes = engine_conf->code_size;

	int eccsteps = engine_conf->nsteps;

	int eccsteps = nand->ecc.ctx.nsteps;

	u8 *ecccalc = engine_conf->calc_buf;

	u8 *ecccode = engine_conf->code_buf;

	unsigned int max_bitflips = 0;
@@ -365,7 +365,7 @@ static int nand_ecc_sw_bch_finish_io_req(struct nand_device *nand, 
		nand_ecc_sw_bch_calculate(nand, data, &ecccalc[i]);



	/* Finish a page read: compare and correct */

	for (eccsteps = engine_conf->nsteps, i = 0, data = req->databuf.in;

	for (eccsteps = nand->ecc.ctx.nsteps, i = 0, data = req->databuf.in;

	     eccsteps;

	     eccsteps--, i += eccbytes, data += eccsize) {

		int stat =  nand_ecc_sw_bch_correct(nand, data,