Commit ef1ce8e9 authored by Kan Liang's avatar Kan Liang Committed by Yunying Sun
Browse files

perf/x86/uncore: Apply the unit control RB tree to MMIO uncore units 

mainline inclusion
from mainline-v6.11-rc1
commit 80580dae65b941eb681bd79f31f64f91b58232b4
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IAGJQ7
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=80580dae65b941eb681bd79f31f64f91b58232b4



-------------------------------------

The unit control RB tree has the unit control and unit ID information
for all the units. Use it to replace the box_ctls/mmio_offsets to get
an accurate unit control address for MMIO uncore units.

Intel-SIG: commit 80580dae65b9 perf/x86/uncore: Apply the unit control RB tree to MMIO uncore units
Backport SPR/EMR CXL and HBM perfmon support to kernel v5.10

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: default avatarYunying Sun <yunying.sun@intel.com>
Link: https://lore.kernel.org/r/20240614134631.1092359-5-kan.liang@linux.intel.com


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent aa4b1617

arch/x86/events/intel/uncore_discovery.c

+14 −16
Original line number Diff line number Diff line
@@ -598,34 +598,30 @@ static struct intel_uncore_ops generic_uncore_pci_ops = { 


#define UNCORE_GENERIC_MMIO_SIZE		0x4000



static unsigned int generic_uncore_mmio_box_ctl(struct intel_uncore_box *box)

{

	struct intel_uncore_type *type = box->pmu->type;



	if (!type->box_ctls || !type->box_ctls[box->dieid] || !type->mmio_offsets)

		return 0;



	return type->box_ctls[box->dieid] + type->mmio_offsets[box->pmu->pmu_idx];

}



void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box)

{

	unsigned int box_ctl = generic_uncore_mmio_box_ctl(box);

	static struct intel_uncore_discovery_unit *unit;

	struct intel_uncore_type *type = box->pmu->type;

	resource_size_t addr;



	if (!box_ctl) {

	unit = intel_uncore_find_discovery_unit(type->boxes, box->dieid, box->pmu->pmu_idx);

	if (!unit) {

		pr_warn("Uncore type %d id %d: Cannot find box control address.\n",

			type->type_id, box->pmu->pmu_idx);

		return;

	}



	if (!unit->addr) {

		pr_warn("Uncore type %d box %d: Invalid box control address.\n",

			type->type_id, type->box_ids[box->pmu->pmu_idx]);

			type->type_id, unit->id);

		return;

	}



	addr = box_ctl;

	addr = unit->addr;

	box->io_addr = ioremap(addr, UNCORE_GENERIC_MMIO_SIZE);

	if (!box->io_addr) {

		pr_warn("Uncore type %d box %d: ioremap error for 0x%llx.\n",

			type->type_id, type->box_ids[box->pmu->pmu_idx],

			(unsigned long long)addr);

			type->type_id, unit->id, (unsigned long long)addr);

		return;

	}
@@ -714,6 +710,8 @@ static bool uncore_update_uncore_type(enum uncore_access_type type_id, 
		uncore->box_ctls = type->box_ctrl_die;

		uncore->mmio_offsets = type->box_offset;

		uncore->mmio_map_size = UNCORE_GENERIC_MMIO_SIZE;

		uncore->boxes = &type->units;

		uncore->num_boxes = type->num_units;

		break;

	default:

		return false;