Commit ef0beba1 authored by Luca Weiss's avatar Luca Weiss Committed by Linus Walleij
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pinctrl: qcom: sm6350: fix order of UFS & SDC pins



In other places the SDC and UFS pins have been swapped but this was
missed in the PINCTRL_PIN definitions. Fix that.

Fixes: 7d74b55a ("pinctrl: qcom: Add SM6350 pinctrl driver")
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20220318183004.858707-5-luca.weiss@fairphone.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent fda4d7e7
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+8 −8
Original line number Diff line number Diff line
@@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = {
	PINCTRL_PIN(153, "GPIO_153"),
	PINCTRL_PIN(154, "GPIO_154"),
	PINCTRL_PIN(155, "GPIO_155"),
	PINCTRL_PIN(156, "SDC1_RCLK"),
	PINCTRL_PIN(157, "SDC1_CLK"),
	PINCTRL_PIN(158, "SDC1_CMD"),
	PINCTRL_PIN(159, "SDC1_DATA"),
	PINCTRL_PIN(160, "SDC2_CLK"),
	PINCTRL_PIN(161, "SDC2_CMD"),
	PINCTRL_PIN(162, "SDC2_DATA"),
	PINCTRL_PIN(163, "UFS_RESET"),
	PINCTRL_PIN(156, "UFS_RESET"),
	PINCTRL_PIN(157, "SDC1_RCLK"),
	PINCTRL_PIN(158, "SDC1_CLK"),
	PINCTRL_PIN(159, "SDC1_CMD"),
	PINCTRL_PIN(160, "SDC1_DATA"),
	PINCTRL_PIN(161, "SDC2_CLK"),
	PINCTRL_PIN(162, "SDC2_CMD"),
	PINCTRL_PIN(163, "SDC2_DATA"),
};

#define DECLARE_MSM_GPIO_PINS(pin) \