Commit eed280df authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add memory controller on Tegra234 



This adds the memory controller and the embedded external memory
controller found on the Tegra234 SoC.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent cc939667

arch/arm64/boot/dts/nvidia/tegra234.dtsi

+49 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <dt-bindings/clock/tegra234-clock.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/tegra186-hsp.h>

#include <dt-bindings/memory/tegra234-mc.h>

#include <dt-bindings/reset/tegra234-reset.h>



/ {
@@ -84,6 +85,54 @@ 
			gpio-controller;

		};



		mc: memory-controller@2c00000 {

			compatible = "nvidia,tegra234-mc";

			reg = <0x02c00000 0x100000>,

			      <0x02b80000 0x040000>,

			      <0x01700000 0x100000>;

			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

			#interconnect-cells = <1>;

			status = "okay";



			#address-cells = <2>;

			#size-cells = <2>;



			ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,

				 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,

				 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;



			/*

			 * Bit 39 of addresses passing through the memory

			 * controller selects the XBAR format used when memory

			 * is accessed. This is used to transparently access

			 * memory in the XBAR format used by the discrete GPU

			 * (bit 39 set) or Tegra (bit 39 clear).

			 *

			 * As a consequence, the operating system must ensure

			 * that bit 39 is never used implicitly, for example

			 * via an I/O virtual address mapping of an IOMMU. If

			 * devices require access to the XBAR switch, their

			 * drivers must set this bit explicitly.

			 *

			 * Limit the DMA range for memory clients to [38:0].

			 */

			dma-ranges = <0x0 0x0 0x0 0x80 0x0>;



			emc: external-memory-controller@2c60000 {

				compatible = "nvidia,tegra234-emc";

				reg = <0x0 0x02c60000 0x0 0x90000>,

				      <0x0 0x01780000 0x0 0x80000>;

				interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA234_CLK_EMC>;

				clock-names = "emc";

				status = "okay";



				#interconnect-cells = <0>;



				nvidia,bpmp = <&bpmp>;

			};

		};



		uarta: serial@3100000 {

			compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";

			reg = <0x03100000 0x10000>;