Commit eec51ab2 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc8280xp: Add GPU related nodes 



Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.

Tested-by: default avatarSteev Klimaszewski <steev@kali.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: default avatarBjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230614142204.2675653-2-quic_bjorande@quicinc.com
parent ecbfba69

arch/arm64/boot/dts/qcom/sa8540p.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -167,6 +167,14 @@ 
	};

};



&gpucc {

	status = "disabled";

};



&gpu_smmu {

	status = "disabled";

};



&pcie2a {

	compatible = "qcom,pcie-sa8540p";

arch/arm64/boot/dts/qcom/sc8280xp.dtsi

+175 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 


#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>

#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>

#include <dt-bindings/interconnect/qcom,osm-l3.h>
@@ -2332,6 +2333,180 @@ 
			reg = <0x0 0x01fc0000 0x0 0x30000>;

		};



		gpu: gpu@3d00000 {

			compatible = "qcom,adreno-690.0", "qcom,adreno";



			reg = <0 0x03d00000 0 0x40000>,

			      <0 0x03d9e000 0 0x1000>,

			      <0 0x03d61000 0 0x800>;

			reg-names = "kgsl_3d0_reg_memory",

				    "cx_mem",

				    "cx_dbgc";

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;

			operating-points-v2 = <&gpu_opp_table>;



			qcom,gmu = <&gmu>;

			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;

			interconnect-names = "gfx-mem";

			#cooling-cells = <2>;



			status = "disabled";



			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-270000000 {

					opp-hz = /bits/ 64 <270000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					opp-peak-kBps = <451000>;

				};



				opp-410000000 {

					opp-hz = /bits/ 64 <410000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					opp-peak-kBps = <1555000>;

				};



				opp-500000000 {

					opp-hz = /bits/ 64 <500000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					opp-peak-kBps = <1555000>;

				};



				opp-547000000 {

					opp-hz = /bits/ 64 <547000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;

					opp-peak-kBps = <1555000>;

				};



				opp-606000000 {

					opp-hz = /bits/ 64 <606000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					opp-peak-kBps = <2736000>;

				};



				opp-640000000 {

					opp-hz = /bits/ 64 <640000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

					opp-peak-kBps = <2736000>;

				};



				opp-655000000 {

					opp-hz = /bits/ 64 <655000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

					opp-peak-kBps = <2736000>;

				};



				opp-690000000 {

					opp-hz = /bits/ 64 <690000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

					opp-peak-kBps = <2736000>;

				};

			};

		};



		gmu: gmu@3d6a000 {

			compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";

			reg = <0 0x03d6a000 0 0x34000>,

			      <0 0x03de0000 0 0x10000>,

			      <0 0x0b290000 0 0x10000>;

			reg-names = "gmu", "rscc", "gmu_pdc";

			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hfi", "gmu";

			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_CXO_CLK>,

				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gpucc GPU_CC_AHB_CLK>,

				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,

				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

			clock-names = "gmu",

				      "cxo",

				      "axi",

				      "memnoc",

				      "ahb",

				      "hub",

				      "smmu_vote";

			power-domains = <&gpucc GPU_CC_CX_GDSC>,

					<&gpucc GPU_CC_GX_GDSC>;

			power-domain-names = "cx",

					     "gx";

			iommus = <&gpu_smmu 5 0xc00>;

			operating-points-v2 = <&gmu_opp_table>;



			gmu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

				};



				opp-500000000 {

					opp-hz = /bits/ 64 <500000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

				};

			};

		};



		gpucc: clock-controller@3d90000 {

			compatible = "qcom,sc8280xp-gpucc";

			reg = <0 0x03d90000 0 0x9000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,

				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

			clock-names = "bi_tcxo",

				      "gcc_gpu_gpll0_clk_src",

				      "gcc_gpu_gpll0_div_clk_src";



			power-domains = <&rpmhpd SC8280XP_GFX>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		gpu_smmu: iommu@3da0000 {

			compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",

				     "qcom,smmu-500", "arm,mmu-500";

			reg = <0 0x03da0000 0 0x20000>;

			#iommu-cells = <2>;

			#global-interrupts = <2>;

			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

				 <&gpucc GPU_CC_AHB_CLK>,

				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,

				 <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,

				 <&gpucc GPU_CC_HUB_AON_CLK>;

			clock-names = "gcc_gpu_memnoc_gfx_clk",

				      "gcc_gpu_snoc_dvm_gfx_clk",

				      "gpu_cc_ahb_clk",

				      "gpu_cc_hlos1_vote_gpu_smmu_clk",

				      "gpu_cc_cx_gmu_clk",

				      "gpu_cc_hub_cx_int_clk",

				      "gpu_cc_hub_aon_clk";



			power-domains = <&gpucc GPU_CC_CX_GDSC>;

			dma-coherent;

		};



		usb_0_hsphy: phy@88e5000 {

			compatible = "qcom,sc8280xp-usb-hs-phy",

				     "qcom,usb-snps-hs-5nm-phy";