Unverified Commit ee95e701 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!365 net: hns3: Some bugfix about L3E check, promisc mode update, FD counter... 

!365 net: hns3: Some bugfix about L3E check, promisc mode update, FD counter rules and rss config for HNS3

Merge Pull Request from: @svishen 
 
This PR is to backport upstream fix for hns3

patch:
net: hns3: add interrupts re-initialization while doing VF FLR
net: hns3: fix miss L3E checking for rx packet
net: hns3: fix VF promisc mode not update when mac table full
net: hns3: fix wrong use of rss size during VF rss config
net: hns3: add support for FD counter

issue:
https://gitee.com/openeuler/kernel/issues/I6A42Q

 
 
Link:https://gitee.com/openeuler/kernel/pulls/365

 

Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Reviewed-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 2da4a932 26837e36

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+4 −6
Original line number Diff line number Diff line
@@ -3935,18 +3935,16 @@ static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 
	return 0;

}



static bool hns3_checksum_complete(struct hns3_enet_ring *ring,

static void hns3_checksum_complete(struct hns3_enet_ring *ring,

				   struct sk_buff *skb, u32 ptype, u16 csum)

{

	if (ptype == HNS3_INVALID_PTYPE ||

	    hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)

		return false;

		return;



	hns3_ring_stats_update(ring, csum_complete);

	skb->ip_summed = CHECKSUM_COMPLETE;

	skb->csum = csum_unfold((__force __sum16)csum);



	return true;

}



static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
@@ -4006,8 +4004,7 @@ static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 
		ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,

					HNS3_RXD_PTYPE_S);



	if (hns3_checksum_complete(ring, skb, ptype, csum))

		return;

	hns3_checksum_complete(ring, skb, ptype, csum);



	/* check if hardware has done checksum */

	if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
@@ -4016,6 +4013,7 @@ static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 
	if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |

				 BIT(HNS3_RXD_OL3E_B) |

				 BIT(HNS3_RXD_OL4E_B)))) {

		skb->ip_summed = CHECKSUM_NONE;

		hns3_ring_stats_update(ring, l3l4_csum_err);



		return;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+6 −4
Original line number Diff line number Diff line
@@ -721,11 +721,11 @@ struct hclge_fd_tcam_config_3_cmd { 


#define HCLGE_FD_AD_DROP_B		0

#define HCLGE_FD_AD_DIRECT_QID_B	1

#define HCLGE_FD_AD_QID_S		2

#define HCLGE_FD_AD_QID_M		GENMASK(11, 2)

#define HCLGE_FD_AD_QID_L_S		2

#define HCLGE_FD_AD_QID_L_M		GENMASK(11, 2)

#define HCLGE_FD_AD_USE_COUNTER_B	12

#define HCLGE_FD_AD_COUNTER_NUM_S	13

#define HCLGE_FD_AD_COUNTER_NUM_M	GENMASK(20, 13)

#define HCLGE_FD_AD_COUNTER_NUM_L_S	13

#define HCLGE_FD_AD_COUNTER_NUM_L_M	GENMASK(19, 13)

#define HCLGE_FD_AD_NXT_STEP_B		20

#define HCLGE_FD_AD_NXT_KEY_S		21

#define HCLGE_FD_AD_NXT_KEY_M		GENMASK(25, 21)
@@ -735,6 +735,8 @@ struct hclge_fd_tcam_config_3_cmd { 
#define HCLGE_FD_AD_TC_OVRD_B		16

#define HCLGE_FD_AD_TC_SIZE_S		17

#define HCLGE_FD_AD_TC_SIZE_M		GENMASK(20, 17)

#define HCLGE_FD_AD_QID_H_B		21

#define HCLGE_FD_AD_COUNTER_NUM_H_B	26



struct hclge_fd_ad_config_cmd {

	u8 stage;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+52 −36
Original line number Diff line number Diff line
@@ -5773,6 +5773,8 @@ static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 
static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,

			      struct hclge_fd_ad_data *action)

{

#define HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2	128



	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);

	struct hclge_fd_ad_config_cmd *req;

	struct hclge_desc desc;
@@ -5799,14 +5801,17 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 
	hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,

		      action->forward_to_direct_queue);

	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,

	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S,

			action->queue_id);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);

	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,

			HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);

	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_L_M,

			HCLGE_FD_AD_COUNTER_NUM_L_S, action->counter_id);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);

	hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,

			action->counter_id);

			action->next_input_key);

	hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B,

		      action->queue_id >= HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 ?

		      1 : 0);



	req->ad_data = cpu_to_le64(ad_data);

	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
@@ -13487,60 +13492,71 @@ static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 
	return ret;

}



static void hclge_sync_promisc_mode(struct hclge_dev *hdev)

static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport)

{

	struct hclge_vport *vport = &hdev->vport[0];

	struct hnae3_handle *handle = &vport->nic;

	struct hclge_dev *hdev = vport->back;

	bool uc_en = false;

	bool mc_en = false;

	u8 tmp_flags;

	bool bc_en;

	int ret;

	u16 i;



	if (vport->last_promisc_flags != vport->overflow_promisc_flags) {

		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);

		vport->last_promisc_flags = vport->overflow_promisc_flags;

	}



	if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) {

	if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,

				&vport->state))

		return 0;



	/* for PF */

	if (!vport->vport_id) {

		tmp_flags = handle->netdev_flags | vport->last_promisc_flags;

		ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,

					     tmp_flags & HNAE3_MPE);

		if (!ret) {

			clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,

				  &vport->state);

		if (!ret)

			set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,

				&vport->state);

		else

			set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,

				&vport->state);

		return ret;

	}

	}



	for (i = 1; i < hdev->num_alloc_vport; i++) {

		bool uc_en = false;

		bool mc_en = false;

		bool bc_en;



		vport = &hdev->vport[i];



		if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,

					&vport->state))

			continue;



	/* for VF */

	if (vport->vf_info.trusted) {

		uc_en = vport->vf_info.request_uc_en > 0 ||

				vport->overflow_promisc_flags &

				HNAE3_OVERFLOW_UPE;

			vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE;

		mc_en = vport->vf_info.request_mc_en > 0 ||

				vport->overflow_promisc_flags &

				HNAE3_OVERFLOW_MPE;

			vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE;

	}

	bc_en = vport->vf_info.request_bc_en > 0;



	ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,

					 mc_en, bc_en);

	if (ret) {

			set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,

				&vport->state);

			return;

		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);

		return ret;

	}

	hclge_set_vport_vlan_fltr_change(vport);



	return 0;

}



static void hclge_sync_promisc_mode(struct hclge_dev *hdev)

{

	struct hclge_vport *vport;

	int ret;

	u16 i;



	for (i = 0; i < hdev->num_alloc_vport; i++) {

		vport = &hdev->vport[i];



		ret = hclge_sync_vport_promisc_mode(vport);

		if (ret)

			return;

	}

}

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

+3 −2
Original line number Diff line number Diff line
@@ -2837,7 +2837,8 @@ static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 
	struct pci_dev *pdev = hdev->pdev;

	int ret = 0;



	if (hdev->reset_type == HNAE3_VF_FULL_RESET &&

	if ((hdev->reset_type == HNAE3_VF_FULL_RESET ||

	     hdev->reset_type == HNAE3_FLR_RESET) &&

	    test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {

		hclgevf_misc_irq_uninit(hdev);

		hclgevf_uninit_msi(hdev);
@@ -3201,7 +3202,7 @@ static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 


	hclgevf_update_rss_size(handle, new_tqps_num);



	hclge_comm_get_rss_tc_info(cur_rss_size, hdev->hw_tc_map,

	hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map,

				   tc_offset, tc_valid, tc_size);

	ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,

					 tc_valid, tc_size);