Loading sound/soc/codecs/rt5682.h +12 −12 Original line number Diff line number Diff line Loading @@ -849,18 +849,18 @@ #define RT5682_SCLK_SRC_PLL2 (0x2 << 13) #define RT5682_SCLK_SRC_SDW (0x3 << 13) #define RT5682_SCLK_SRC_RCCLK (0x4 << 13) #define RT5682_PLL1_SRC_MASK (0x3 << 10) #define RT5682_PLL1_SRC_SFT 10 #define RT5682_PLL1_SRC_MCLK (0x0 << 10) #define RT5682_PLL1_SRC_BCLK1 (0x1 << 10) #define RT5682_PLL1_SRC_SDW (0x2 << 10) #define RT5682_PLL1_SRC_RC (0x3 << 10) #define RT5682_PLL2_SRC_MASK (0x3 << 8) #define RT5682_PLL2_SRC_SFT 8 #define RT5682_PLL2_SRC_MCLK (0x0 << 8) #define RT5682_PLL2_SRC_BCLK1 (0x1 << 8) #define RT5682_PLL2_SRC_SDW (0x2 << 8) #define RT5682_PLL2_SRC_RC (0x3 << 8) #define RT5682_PLL2_SRC_MASK (0x3 << 10) #define RT5682_PLL2_SRC_SFT 10 #define RT5682_PLL2_SRC_MCLK (0x0 << 10) #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) #define RT5682_PLL2_SRC_SDW (0x2 << 10) #define RT5682_PLL2_SRC_RC (0x3 << 10) #define RT5682_PLL1_SRC_MASK (0x3 << 8) #define RT5682_PLL1_SRC_SFT 8 #define RT5682_PLL1_SRC_MCLK (0x0 << 8) #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) #define RT5682_PLL1_SRC_SDW (0x2 << 8) #define RT5682_PLL1_SRC_RC (0x3 << 8) Loading Loading
sound/soc/codecs/rt5682.h +12 −12 Original line number Diff line number Diff line Loading @@ -849,18 +849,18 @@ #define RT5682_SCLK_SRC_PLL2 (0x2 << 13) #define RT5682_SCLK_SRC_SDW (0x3 << 13) #define RT5682_SCLK_SRC_RCCLK (0x4 << 13) #define RT5682_PLL1_SRC_MASK (0x3 << 10) #define RT5682_PLL1_SRC_SFT 10 #define RT5682_PLL1_SRC_MCLK (0x0 << 10) #define RT5682_PLL1_SRC_BCLK1 (0x1 << 10) #define RT5682_PLL1_SRC_SDW (0x2 << 10) #define RT5682_PLL1_SRC_RC (0x3 << 10) #define RT5682_PLL2_SRC_MASK (0x3 << 8) #define RT5682_PLL2_SRC_SFT 8 #define RT5682_PLL2_SRC_MCLK (0x0 << 8) #define RT5682_PLL2_SRC_BCLK1 (0x1 << 8) #define RT5682_PLL2_SRC_SDW (0x2 << 8) #define RT5682_PLL2_SRC_RC (0x3 << 8) #define RT5682_PLL2_SRC_MASK (0x3 << 10) #define RT5682_PLL2_SRC_SFT 10 #define RT5682_PLL2_SRC_MCLK (0x0 << 10) #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) #define RT5682_PLL2_SRC_SDW (0x2 << 10) #define RT5682_PLL2_SRC_RC (0x3 << 10) #define RT5682_PLL1_SRC_MASK (0x3 << 8) #define RT5682_PLL1_SRC_SFT 8 #define RT5682_PLL1_SRC_MCLK (0x0 << 8) #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) #define RT5682_PLL1_SRC_SDW (0x2 << 8) #define RT5682_PLL1_SRC_RC (0x3 << 8) Loading