Commit ee7ccd5f authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch 'icc-sm8550-immutable' of... 

Merge branch 'icc-sm8550-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3

Merge the immutable SM8550 interconnect branch, to gain the include file
from the binding.
parents b7f4f697 e6f0d6a3

Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550



maintainers:

  - Abel Vesa <abel.vesa@linaro.org>

  - Neil Armstrong <neil.armstrong@linaro.org>



description: |

  RPMh interconnect providers support system bandwidth requirements through

  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is

  able to communicate with the BCM through the Resource State Coordinator (RSC)

  associated with each execution environment. Provider nodes must point to at

  least one RPMh device child node pertaining to their RSC and each provider

  can map to multiple RPMh resources.



  See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h



properties:

  compatible:

    enum:

      - qcom,sm8550-aggre1-noc

      - qcom,sm8550-aggre2-noc

      - qcom,sm8550-clk-virt

      - qcom,sm8550-cnoc-main

      - qcom,sm8550-config-noc

      - qcom,sm8550-gem-noc

      - qcom,sm8550-lpass-ag-noc

      - qcom,sm8550-lpass-lpiaon-noc

      - qcom,sm8550-lpass-lpicx-noc

      - qcom,sm8550-mc-virt

      - qcom,sm8550-mmss-noc

      - qcom,sm8550-nsp-noc

      - qcom,sm8550-pcie-anoc

      - qcom,sm8550-system-noc



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



allOf:

  - $ref: qcom,rpmh-common.yaml#

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8550-clk-virt

              - qcom,sm8550-mc-virt

    then:

      properties:

        reg: false

    else:

      required:

        - reg



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8550-pcie-anoc

    then:

      properties:

        clocks:

          items:

            - description: aggre-NOC PCIe AXI clock

            - description: cfg-NOC PCIe a-NOC AHB clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8550-aggre1-noc

    then:

      properties:

        clocks:

          items:

            - description: aggre UFS PHY AXI clock

            - description: aggre USB3 PRIM AXI clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8550-aggre2-noc

    then:

      properties:

        clocks:

          items:

            - description: RPMH CC IPA clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8550-aggre1-noc

              - qcom,sm8550-aggre2-noc

              - qcom,sm8550-pcie-anoc

    then:

      required:

        - clocks

    else:

      properties:

        clocks: false



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8550-gcc.h>



    clk_virt: interconnect-0 {

      compatible = "qcom,sm8550-clk-virt";

      #interconnect-cells = <2>;

      qcom,bcm-voters = <&apps_bcm_voter>;

    };



    aggre1_noc: interconnect@16e0000 {

      compatible = "qcom,sm8550-aggre1-noc";

      reg = <0x016e0000 0x14400>;

      #interconnect-cells = <2>;

      clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

               <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;

      qcom,bcm-voters = <&apps_bcm_voter>;

    };

drivers/interconnect/qcom/Kconfig

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@@ -200,5 +200,14 @@ config INTERCONNECT_QCOM_SM8450 
	  This is a driver for the Qualcomm Network-on-Chip on SM8450-based

	  platforms.



config INTERCONNECT_QCOM_SM8550

	tristate "Qualcomm SM8550 interconnect driver"

	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

	select INTERCONNECT_QCOM_RPMH

	select INTERCONNECT_QCOM_BCM_VOTER

	help

	  This is a driver for the Qualcomm Network-on-Chip on SM8550-based

	  platforms.



config INTERCONNECT_QCOM_SMD_RPM

	tristate

drivers/interconnect/qcom/Makefile

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@@ -25,6 +25,7 @@ qnoc-sm8150-objs := sm8150.o 
qnoc-sm8250-objs			:= sm8250.o

qnoc-sm8350-objs			:= sm8350.o

qnoc-sm8450-objs			:= sm8450.o

qnoc-sm8550-objs			:= sm8550.o

icc-smd-rpm-objs			:= smd-rpm.o icc-rpm.o



obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@@ -49,4 +50,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o 
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o

obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

drivers/interconnect/qcom/sm8550.c

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drivers/interconnect/qcom/sm8550.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * SM8450 interconnect IDs

 *

 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021, Linaro Limited

 */



#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H

#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H



#define SM8550_MASTER_A1NOC_SNOC			0

#define SM8550_MASTER_A2NOC_SNOC			1

#define SM8550_MASTER_ANOC_PCIE_GEM_NOC			2

#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0	3

#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1	4

#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2	5

#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP		6

#define SM8550_MASTER_APPSS_PROC			7

#define SM8550_MASTER_CAMNOC_HF				8

#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0		9

#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1		10

#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2		11

#define SM8550_MASTER_CAMNOC_ICP			12

#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0		13

#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1		14

#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2		15

#define SM8550_MASTER_CAMNOC_SF				16

#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0		17

#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1		18

#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2		19

#define SM8550_MASTER_CDSP_HCP				20

#define SM8550_MASTER_CDSP_PROC				21

#define SM8550_MASTER_CNOC_CFG				22

#define SM8550_MASTER_CNOC_MNOC_CFG			23

#define SM8550_MASTER_COMPUTE_NOC			24

#define SM8550_MASTER_CRYPTO				25

#define SM8550_MASTER_GEM_NOC_CNOC			26

#define SM8550_MASTER_GEM_NOC_PCIE_SNOC			27

#define SM8550_MASTER_GFX3D				28

#define SM8550_MASTER_GIC				29

#define SM8550_MASTER_GIC_AHB				30

#define SM8550_MASTER_GPU_TCU				31

#define SM8550_MASTER_IPA				32

#define SM8550_MASTER_LLCC				33

#define SM8550_MASTER_LLCC_CAM_IFE_0			34

#define SM8550_MASTER_LLCC_CAM_IFE_1			35

#define SM8550_MASTER_LLCC_CAM_IFE_2			36

#define SM8550_MASTER_LLCC_DISP				37

#define SM8550_MASTER_LPASS_GEM_NOC			38

#define SM8550_MASTER_LPASS_LPINOC			39

#define SM8550_MASTER_LPASS_PROC			40

#define SM8550_MASTER_LPIAON_NOC			41

#define SM8550_MASTER_MDP				42

#define SM8550_MASTER_MDP_DISP				43

#define SM8550_MASTER_MNOC_HF_MEM_NOC			44

#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0		45

#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1		46

#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2		47

#define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP		48

#define SM8550_MASTER_MNOC_SF_MEM_NOC			49

#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0		50

#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1		51

#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2		52

#define SM8550_MASTER_MSS_PROC				53

#define SM8550_MASTER_PCIE_0				54

#define SM8550_MASTER_PCIE_1				55

#define SM8550_MASTER_PCIE_ANOC_CFG			56

#define SM8550_MASTER_QDSS_BAM				57

#define SM8550_MASTER_QDSS_ETR				58

#define SM8550_MASTER_QDSS_ETR_1			59

#define SM8550_MASTER_QSPI_0				60

#define SM8550_MASTER_QUP_1				61

#define SM8550_MASTER_QUP_2				62

#define SM8550_MASTER_QUP_CORE_0			63

#define SM8550_MASTER_QUP_CORE_1			64

#define SM8550_MASTER_QUP_CORE_2			65

#define SM8550_MASTER_SDCC_2				66

#define SM8550_MASTER_SDCC_4				67

#define SM8550_MASTER_SNOC_GC_MEM_NOC			68

#define SM8550_MASTER_SNOC_SF_MEM_NOC			69

#define SM8550_MASTER_SP				70

#define SM8550_MASTER_SYS_TCU				71

#define SM8550_MASTER_UFS_MEM				72

#define SM8550_MASTER_USB3_0				73

#define SM8550_MASTER_VIDEO				74

#define SM8550_MASTER_VIDEO_CV_PROC			75

#define SM8550_MASTER_VIDEO_PROC			76

#define SM8550_MASTER_VIDEO_V_PROC			77

#define SM8550_SLAVE_A1NOC_SNOC				78

#define SM8550_SLAVE_A2NOC_SNOC				79

#define SM8550_SLAVE_AHB2PHY_NORTH			80

#define SM8550_SLAVE_AHB2PHY_SOUTH			81

#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC			82

#define SM8550_SLAVE_AOSS				83

#define SM8550_SLAVE_APPSS				84

#define SM8550_SLAVE_BOOT_IMEM				85

#define SM8550_SLAVE_CAMERA_CFG				86

#define SM8550_SLAVE_CDSP_MEM_NOC			87

#define SM8550_SLAVE_CLK_CTL				88

#define SM8550_SLAVE_CNOC_CFG				89

#define SM8550_SLAVE_CNOC_MNOC_CFG			90

#define SM8550_SLAVE_CNOC_MSS				91

#define SM8550_SLAVE_CPR_NSPCX				92

#define SM8550_SLAVE_CRYPTO_0_CFG			93

#define SM8550_SLAVE_CX_RDPM				94

#define SM8550_SLAVE_DDRSS_CFG				95

#define SM8550_SLAVE_DISPLAY_CFG			96

#define SM8550_SLAVE_EBI1				97

#define SM8550_SLAVE_EBI1_CAM_IFE_0			98

#define SM8550_SLAVE_EBI1_CAM_IFE_1			99

#define SM8550_SLAVE_EBI1_CAM_IFE_2			100

#define SM8550_SLAVE_EBI1_DISP				101

#define SM8550_SLAVE_GEM_NOC_CNOC			102

#define SM8550_SLAVE_GFX3D_CFG				103

#define SM8550_SLAVE_I2C				104

#define SM8550_SLAVE_IMEM				105

#define SM8550_SLAVE_IMEM_CFG				106

#define SM8550_SLAVE_IPA_CFG				107

#define SM8550_SLAVE_IPC_ROUTER_CFG			108

#define SM8550_SLAVE_LLCC				109

#define SM8550_SLAVE_LLCC_CAM_IFE_0			110

#define SM8550_SLAVE_LLCC_CAM_IFE_1			111

#define SM8550_SLAVE_LLCC_CAM_IFE_2			112

#define SM8550_SLAVE_LLCC_DISP				113

#define SM8550_SLAVE_LPASS_GEM_NOC			114

#define SM8550_SLAVE_LPASS_QTB_CFG			115

#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC		116

#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC		117

#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC			118

#define SM8550_SLAVE_MNOC_HF_MEM_NOC			119

#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0		120

#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1		121

#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2		122

#define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP		123

#define SM8550_SLAVE_MNOC_SF_MEM_NOC			124

#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0		125

#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1		126

#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2		127

#define SM8550_SLAVE_MX_RDPM				128

#define SM8550_SLAVE_NSP_QTB_CFG			129

#define SM8550_SLAVE_PCIE_0				130

#define SM8550_SLAVE_PCIE_0_CFG				131

#define SM8550_SLAVE_PCIE_1				132

#define SM8550_SLAVE_PCIE_1_CFG				133

#define SM8550_SLAVE_PCIE_ANOC_CFG			134

#define SM8550_SLAVE_PDM				135

#define SM8550_SLAVE_PIMEM_CFG				136

#define SM8550_SLAVE_PRNG				137

#define SM8550_SLAVE_QDSS_CFG				138

#define SM8550_SLAVE_QDSS_STM				139

#define SM8550_SLAVE_QSPI_0				140

#define SM8550_SLAVE_QUP_1				141

#define SM8550_SLAVE_QUP_2				142

#define SM8550_SLAVE_QUP_CORE_0				143

#define SM8550_SLAVE_QUP_CORE_1				144

#define SM8550_SLAVE_QUP_CORE_2				145

#define SM8550_SLAVE_RBCPR_CX_CFG			146

#define SM8550_SLAVE_RBCPR_MMCX_CFG			147

#define SM8550_SLAVE_RBCPR_MXA_CFG			148

#define SM8550_SLAVE_RBCPR_MXC_CFG			149

#define SM8550_SLAVE_SDCC_2				150

#define SM8550_SLAVE_SDCC_4				151

#define SM8550_SLAVE_SERVICE_MNOC			152

#define SM8550_SLAVE_SERVICE_PCIE_ANOC			153

#define SM8550_SLAVE_SNOC_GEM_NOC_GC			154

#define SM8550_SLAVE_SNOC_GEM_NOC_SF			155

#define SM8550_SLAVE_SPSS_CFG				156

#define SM8550_SLAVE_TCSR				157

#define SM8550_SLAVE_TCU				158

#define SM8550_SLAVE_TLMM				159

#define SM8550_SLAVE_TME_CFG				160

#define SM8550_SLAVE_UFS_MEM_CFG			161

#define SM8550_SLAVE_USB3_0				162

#define SM8550_SLAVE_VENUS_CFG				163

#define SM8550_SLAVE_VSENSE_CTRL_CFG			164



#endif