Merge branch 'clk-unused' into clk-next

* Clock and reset bindings for CSR atlas7

Required properties:

- compatible: Should be "sirf,atlas7-car"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- #reset-cells: Should be <1>

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.

The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c

The reset consumer should specify the desired reset by having the reset

ID in its "reset" phandle cell.

The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c

Examples: Clock and reset controller node:

car: clock-controller@18620000 {

	compatible = "sirf,atlas7-car";

	reg = <0x18620000 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Examples: Consumers using clock or reset:

timer@10dc0000 {

	compatible = "sirf,macro-tick";

	reg = <0x10dc0000 0x1000>;

	clocks = <&car 54>;

	interrupts = <0 0 0>,

		   <0 1 0>,

		   <0 2 0>,

		   <0 49 0>,

		   <0 50 0>,

		   <0 51 0>;

};

uart1: uart@18020000 {

	cell-index = <1>;

	compatible = "sirf,macro-uart";

	reg = <0x18020000 0x1000>;

	clocks = <&clks 95>;

	interrupts = <0 18 0>;

	fifosize = <32>;

};

vpp@13110000 {

	compatible = "sirf,prima2-vpp";

	reg = <0x13110000 0x10000>;

	interrupts = <0 31 0>;

	clocks = <&car 85>;

	resets = <&car 29>;

};

* Clock bindings for CSR SiRFprimaII

Required properties:

- compatible: Should be "sirf,prima2-clkc"

- reg: Address and length of the register set

- interrupts: Should contain clock controller interrupt

- #clock-cells: Should be <1>

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of prima2

clocks and IDs.

	Clock			ID

	---------------------------

	rtc			0

	osc             	1

	pll1            	2

	pll2            	3

	pll3            	4

	mem             	5

	sys             	6

	security        	7

	dsp             	8

	gps             	9

	mf              	10

	io              	11

	cpu             	12

	uart0           	13

	uart1           	14

	uart2           	15

	tsc             	16

	i2c0            	17

	i2c1            	18

	spi0            	19

	spi1            	20

	pwmc            	21

	efuse           	22

	pulse           	23

	dmac0           	24

	dmac1           	25

	nand            	26

	audio           	27

	usp0            	28

	usp1            	29

	usp2            	30

	vip             	31

	gfx             	32

	mm              	33

	lcd             	34

	vpp             	35

	mmc01           	36

	mmc23           	37

	mmc45           	38

	usbpll          	39

	usb0            	40

	usb1			41

Examples:

clks: clock-controller@88000000 {

	compatible = "sirf,prima2-clkc";

	reg = <0x88000000 0x1000>;

	interrupts = <3>;

	#clock-cells = <1>;

};

i2c0: i2c@b00e0000 {

	cell-index = <0>;

	compatible = "sirf,prima2-i2c";

	reg = <0xb00e0000 0x10000>;

	interrupts = <24>;

	clocks = <&clks 17>;

};

Clock bindings for ST-Ericsson U300 System Controller Clocks

Bindings for the gated system controller clocks:

Required properties:

- compatible: must be "stericsson,u300-syscon-clk"

- #clock-cells: must be <0>

- clock-type: specifies the type of clock:

  0 = slow clock

  1 = fast clock

  2 = rest/remaining clock

- clock-id: specifies the clock in the type range

Optional properties:

- clocks: parent clock(s)

The available clocks per type are as follows:

Type:  ID:   Clock:

-------------------

0      0     Slow peripheral bridge clock

0      1     UART0 clock

0      4     GPIO clock

0      6     RTC clock

0      7     Application timer clock

0      8     Access timer clock

1      0     Fast peripheral bridge clock

1      1     I2C bus 0 clock

1      2     I2C bus 1 clock

1      5     MMC interface peripheral (silicon) clock

1      6     SPI clock

2      3     CPU clock

2      4     DMA controller clock

2      5     External Memory Interface (EMIF) clock

2      6     NAND flask interface clock

2      8     XGAM graphics engine clock

2      9     Shared External Memory Interface (SEMI) clock

2      10    AHB Subsystem Bridge clock

2      12    Interrupt controller clock

Example:

gpio_clk: gpio_clk@13M {

	#clock-cells = <0>;

	compatible = "stericsson,u300-syscon-clk";

	clock-type = <0>; /* Slow */

	clock-id = <4>;

	clocks = <&slow_clk>;

};

gpio: gpio@c0016000 {

	compatible = "stericsson,gpio-coh901";

	(...)

	clocks = <&gpio_clk>;

};

Bindings for the MMC/SD card clock:

Required properties:

- compatible: must be "stericsson,u300-syscon-mclk"

- #clock-cells: must be <0>

Optional properties:

- clocks: parent clock(s)

mmc_mclk: mmc_mclk {

	#clock-cells = <0>;

	compatible = "stericsson,u300-syscon-mclk";

	clocks = <&mmc_pclk>;

};

mmcsd: mmcsd@c0001000 {

	compatible = "arm,pl18x", "arm,primecell";

	clocks = <&mmc_pclk>, <&mmc_mclk>;

	clock-names = "apb_pclk", "mclk";

	(...)

};

* Sigma Designs Tango4 Clock Generator

The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used

for RAM and various peripheral devices). The clock binding described here

is applicable to all Tango4 SoCs.

Required Properties:

- compatible: should be "sigma,tango4-clkgen".

- reg: physical base address of the device and length of memory mapped region.

- clocks: phandle of the input clock (crystal oscillator).

- clock-output-names: should be "cpuclk" and "sysclk".

- #clock-cells: should be set to 1.

Example:

	clkgen: clkgen@10000 {

		compatible = "sigma,tango4-clkgen";

		reg = <0x10000 0x40>;

		clocks = <&xtal>;

		clock-output-names = "cpuclk", "sysclk";

		#clock-cells = <1>;

	};

Device Tree Clock bindings for ZTE zx296702

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible : shall be one of the following:

	"zte,zx296702-topcrm-clk":

		zx296702 top clock selection, divider and gating

	"zte,zx296702-lsp0crpm-clk" and

	"zte,zx296702-lsp1crpm-clk":

		zx296702 device level clock selection and gating

- reg: Address and length of the register set

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h

for the full list of zx296702 clock IDs.

topclk: topcrm@09800000 {

        compatible = "zte,zx296702-topcrm-clk";

        reg = <0x09800000 0x1000>;

        #clock-cells = <1>;

};

uart0: serial@09405000 {

        compatible = "zte,zx296702-uart";

        reg = <0x09405000 0x1000>;

        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&lsp1clk ZX296702_UART0_PCLK>;

};