Commit ee421bb4 authored by Ashutosh Dixit's avatar Ashutosh Dixit Committed by Tvrtko Ursulin
Browse files

drm/i915/pcode: Extend pcode functions for multiple gt's 



Each gt contains an independent instance of pcode. Extend pcode functions
to interface with pcode on different gt's. To avoid creating dependency of
display functionality on intel_gt, pcode function interfaces are exposed in
terms of uncore rather than intel_gt. Callers have been converted to pass
in the appropritate (i915 or intel_gt) uncore to the pcode functions.

v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo)
v3: Retain previous function names to eliminate needless #defines (Rodrigo)
v4: Move out i915_pcode_init() to a separate patch (Tvrtko)
    Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-2-tvrtko.ursulin@linux.intel.com
[tursulin: fixup merge conflict]
parent 85a040bc

drivers/gpu/drm/i915/display/hsw_ips.c

+2 −2
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 


	if (IS_BROADWELL(i915)) {

		drm_WARN_ON(&i915->drm,

			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL,

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,

					    IPS_ENABLE | IPS_PCODE_CONTROL));

		/*

		 * Quoting Art Runyan: "its not safe to expect any particular
@@ -62,7 +62,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) 


	if (IS_BROADWELL(i915)) {

		drm_WARN_ON(&i915->drm,

			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));

		/*

		 * Wait for PCODE to finish disabling IPS. The BSpec specified

		 * 42ms timeout value leads to occasional timeouts so use 100ms

drivers/gpu/drm/i915/display/intel_bw.c

+3 −3
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 
	u16 dclk;

	int ret;



	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

			     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),

			     &val, &val2);

	if (ret)
@@ -104,7 +104,7 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv, 
	int ret;

	int i;



	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

	ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

			     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);

	if (ret)

		return ret;
@@ -123,7 +123,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, 
	int ret;



	/* bspec says to keep retrying for at least 1 ms */

	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,

	ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,

				points_mask,

				ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,

				ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,

drivers/gpu/drm/i915/display/intel_cdclk.c

+8 −8
Original line number Diff line number Diff line
@@ -800,7 +800,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
		     "trying to change cdclk frequency with cdclk not enabled\n"))

		return;



	ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

	ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

	if (ret) {

		drm_err(&dev_priv->drm,

			"failed to inform pcode about cdclk change\n");
@@ -828,7 +828,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))

		drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");



	snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,

	snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,

			cdclk_config->voltage_level);



	intel_de_write(dev_priv, CDCLK_FREQ,
@@ -1086,7 +1086,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
	drm_WARN_ON_ONCE(&dev_priv->drm,

			 IS_SKYLAKE(dev_priv) && vco == 8640000);



	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,

	ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,

				SKL_CDCLK_PREPARE_FOR_CHANGE,

				SKL_CDCLK_READY_FOR_CHANGE,

				SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1132,7 +1132,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
	intel_de_posting_read(dev_priv, CDCLK_CTL);



	/* inform PCU of the change */

	snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

	snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,

			cdclk_config->voltage_level);



	intel_update_cdclk(dev_priv);
@@ -1702,7 +1702,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 


	/* Inform power controller of upcoming frequency change. */

	if (DISPLAY_VER(dev_priv) >= 11)

		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,

		ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,

					SKL_CDCLK_PREPARE_FOR_CHANGE,

					SKL_CDCLK_READY_FOR_CHANGE,

					SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1711,7 +1711,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		 * BSpec requires us to wait up to 150usec, but that leads to

		 * timeouts; the 2ms used here is based on experiment.

		 */

		ret = snb_pcode_write_timeout(dev_priv,

		ret = snb_pcode_write_timeout(&dev_priv->uncore,

					      HSW_PCODE_DE_WRITE_FREQ_REQ,

					      0x80000000, 150, 2);

	if (ret) {
@@ -1774,7 +1774,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));



	if (DISPLAY_VER(dev_priv) >= 11) {

		ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,

				      cdclk_config->voltage_level);

	} else {

		/*
@@ -1783,7 +1783,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		 * FIXME: Waiting for the request completion could be delayed

		 * until the next PCODE request based on BSpec.

		 */

		ret = snb_pcode_write_timeout(dev_priv,

		ret = snb_pcode_write_timeout(&dev_priv->uncore,

					      HSW_PCODE_DE_WRITE_FREQ_REQ,

					      cdclk_config->voltage_level,

					      150, 2);

drivers/gpu/drm/i915/display/intel_display_power.c

+1 −1
Original line number Diff line number Diff line
@@ -1196,7 +1196,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) 
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)

{

	if (IS_HASWELL(dev_priv)) {

		if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))

		if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))

			drm_dbg_kms(&dev_priv->drm,

				    "Failed to write to D_COMP\n");

	} else {

drivers/gpu/drm/i915/display/intel_display_power_well.c

+2 −2
Original line number Diff line number Diff line
@@ -474,7 +474,7 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915) 
	int ret, tries = 0;



	while (1) {

		ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,

		ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,

					      250, 1);

		if (ret != -EAGAIN || ++tries == 3)

			break;
@@ -1739,7 +1739,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block) 
		 * Spec states that we should timeout the request after 200us

		 * but the function below will timeout after 500us

		 */

		ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);

		ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);

		if (ret == 0) {

			if (block &&

			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))