Unverified Commit ee14a6ef authored by Mark Brown's avatar Mark Brown
Browse files

Merge series "Add Tegra Quad SPI driver" from Sowjanya Komatineni <skomatineni@nvidia.com>: 

This series adds Tegra210, Tegra186, and Tegra194 Quad SPI driver and
enables Quad SPI on Jetson Nano and Jetson Xavier NX.

QSPI controller is available on Tegra210, Tegra186 and Tegra194.

Tegra186 and Tegra194 has additional feature of combined sequence mode
where command, address and data can all be transferred in a single transfer.
Combined sequence mode is useful only when using DMA mode transfer.

This series does not have combined sequence mode feature as Tegra186/Tegra194
GPCDMA driver is not upstreamed yet.

This series includes
- dt-binding document
- QSPI driver for Tegra210/Tegra186/Tegra194
- Enables QSPI on Jetson Nano and Jetson Xavier NX.

Delta between patch versions:
[v5]:	Simplified implementation in Patch-0006

[v4]:	Updated dummy cycles implementation based on v3 feedback
	- Added dummy_data bit field int spi_transfer to indicate corresponding
	  transfer is dummy bytes transfer.
	- Updated Tegra QSPI transfer_one_message to identify dummy transfer and
	  to use HW supported dummy bytes transfer when dummy cycles are with in
	  Tegra QSPI supported max HW dummy cycles otherwise fallsback to transfer
	  dummy bytes from software.
	- Updated dt-bindings based on v3 feedback.

[v3]:	v2 has some mixed patches sent out accidentally.
	v3 sends proper patches with fixes mentioned in v2.

[v2]:	below v1 feedback
	- Added SPI_MASTER_USES_HW_DUMMY_CYCLES flag for controllers supporting
	  hardware dummy cycles and skips dummy bytes transfer from software for
	  these controllers.
	- Updated dt-binding doc with tx/rx tap delay properties.
	- Added qspi_out clock to dt-binding doc which will be used later with
	  ddr mode support.
	- All other v1 feedback on some cleanup.

Sowjanya Komatineni (9):
  dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
  dt-bindings: spi: Add Tegra Quad SPI device tree binding
  MAINTAINERS: Add Tegra Quad SPI driver section
  spi: tegra210-quad: Add support for Tegra210 QSPI controller
  spi: spi-mem: Mark dummy transfers by setting dummy_data bit
  spi: tegra210-quad: Add support for hardware dummy cycles transfer
  arm64: tegra: Enable QSPI on Jetson Nano
  arm64: tegra: Add QSPI nodes on Tegra194
  arm64: tegra: Enable QSPI on Jetson Xavier NX

 .../bindings/spi/nvidia,tegra210-quad.yaml         |  117 ++
 MAINTAINERS                                        |    8 +
 .../dts/nvidia/tegra194-p3509-0000+p3668-0000.dts  |   12 +
 arch/arm64/boot/dts/nvidia/tegra194.dtsi           |   28 +
 arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts |   12 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi           |    5 +-
 drivers/spi/Kconfig                                |    9 +
 drivers/spi/Makefile                               |    1 +
 drivers/spi/spi-mem.c                              |    1 +
 drivers/spi/spi-tegra210-quad.c                    | 1410 ++++++++++++++++++++
 include/dt-bindings/clock/tegra210-car.h           |    2 +-
 include/linux/spi/spi.h                            |    2 +
 12 files changed, 1604 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
 create mode 100644 drivers/spi/spi-tegra210-quad.c

--
2.7.4
parents f453f293 6a8a8b51

Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Tegra Quad SPI Controller



maintainers:

  - Thierry Reding <thierry.reding@gmail.com>

  - Jonathan Hunter <jonathanh@nvidia.com>



allOf:

  - $ref: "spi-controller.yaml#"



properties:

  compatible:

    enum:

      - nvidia,tegra210-qspi

      - nvidia,tegra186-qspi

      - nvidia,tegra194-qspi



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clock-names:

    items:

      - const: qspi

      - const: qspi_out



  clocks:

    maxItems: 2



  resets:

    maxItems: 1



  dmas:

    maxItems: 2



  dma-names:

    items:

      - const: rx

      - const: tx



patternProperties:

  "@[0-9a-f]+":

    type: object



    properties:

      spi-rx-bus-width:

        enum: [1, 2, 4]



      spi-tx-bus-width:

        enum: [1, 2, 4]



      nvidia,tx-clk-tap-delay:

        description:

          Delays the clock going out to device with this tap value.

          Tap value varies based on platform design trace lengths from Tegra

          QSPI to corresponding slave device.

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 0

        maximum: 31



      nvidia,rx-clk-tap-delay:

        description:

          Delays the clock coming in from the device with this tap value.

          Tap value varies based on platform design trace lengths from Tegra

          QSPI to corresponding slave device.

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 0

        maximum: 255



    required:

      - reg



required:

  - compatible

  - reg

  - interrupts

  - clock-names

  - clocks

  - resets



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/tegra210-car.h>

    #include <dt-bindings/reset/tegra210-car.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@70410000 {

            compatible = "nvidia,tegra210-qspi";

            reg = <0x70410000 0x1000>;

            interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

            #address-cells = <1>;

            #size-cells = <0>;

            clocks = <&tegra_car TEGRA210_CLK_QSPI>,

                     <&tegra_car TEGRA210_CLK_QSPI_PM>;

            clock-names = "qspi", "qspi_out";

            resets = <&tegra_car 211>;

            dmas = <&apbdma 5>, <&apbdma 5>;

            dma-names = "rx", "tx";



            flash@0 {

                    compatible = "spi-nor";

                    reg = <0>;

                    spi-max-frequency = <104000000>;

                    spi-tx-bus-width = <2>;

                    spi-rx-bus-width = <2>;

                    nvidia,tx-clk-tap-delay = <0>;

                    nvidia,rx-clk-tap-delay = <0>;

            };

    };

MAINTAINERS

+8 −0
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@@ -17498,6 +17498,14 @@ M: Laxman Dewangan <ldewangan@nvidia.com> 
S:	Supported

F:	drivers/spi/spi-tegra*









TEGRA QUAD SPI DRIVER









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Jonathan Hunter <jonathanh@nvidia.com>









M:	Sowjanya Komatineni <skomatineni@nvidia.com>









L:	linux-tegra@vger.kernel.org









S:	Maintained









F:	drivers/spi/spi-tegra210-quad.c

















TEGRA VIDEO DRIVER









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Jonathan Hunter <jonathanh@nvidia.com>
































drivers/spi/Kconfig



+9
−0






























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@@ -843,6 +843,15 @@ config SPI_MXS







	help









	  SPI driver for Freescale MXS devices.



















config SPI_TEGRA210_QUAD









	tristate "NVIDIA Tegra QSPI Controller"









	depends on ARCH_TEGRA || COMPILE_TEST









	depends on RESET_CONTROLLER









	help









	  QSPI driver for NVIDIA Tegra QSPI Controller interface. This









	  controller is different from the SPI controller and is available









	  on Tegra SoCs starting from Tegra210.



















config SPI_TEGRA114









	tristate "NVIDIA Tegra114 SPI Controller"









	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
































drivers/spi/Makefile



+1
−0






























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@@ -115,6 +115,7 @@ obj-$(CONFIG_SPI_ST_SSC4)		+= spi-st-ssc4.o







obj-$(CONFIG_SPI_SUN4I)			+= spi-sun4i.o









obj-$(CONFIG_SPI_SUN6I)			+= spi-sun6i.o









obj-$(CONFIG_SPI_SYNQUACER)		+= spi-synquacer.o









obj-$(CONFIG_SPI_TEGRA210_QUAD)		+= spi-tegra210-quad.o









obj-$(CONFIG_SPI_TEGRA114)		+= spi-tegra114.o









obj-$(CONFIG_SPI_TEGRA20_SFLASH)	+= spi-tegra20-sflash.o









obj-$(CONFIG_SPI_TEGRA20_SLINK)		+= spi-tegra20-slink.o
































drivers/spi/spi-mem.c



+1
−0






























Original line number
Diff line number
Diff line







@@ -354,6 +354,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)







		xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;









		xfers[xferpos].len = op->dummy.nbytes;









		xfers[xferpos].tx_nbits = op->dummy.buswidth;









		xfers[xferpos].dummy_data = 1;









		spi_message_add_tail(&xfers[xferpos], &msg);









		xferpos++;









		totalxferlen += op->dummy.nbytes;