Loading drivers/dma/at_hdmac.c +1 −1 Original line number Diff line number Diff line Loading @@ -1320,7 +1320,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, if (unlikely(!is_slave_direction(direction))) goto err_out; if (sconfig->direction == DMA_MEM_TO_DEV) if (direction == DMA_MEM_TO_DEV) reg_width = convert_buswidth(sconfig->dst_addr_width); else reg_width = convert_buswidth(sconfig->src_addr_width); Loading drivers/dma/bcm2835-dma.c +0 −8 Original line number Diff line number Diff line Loading @@ -778,14 +778,6 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan, { struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); if ((cfg->direction == DMA_DEV_TO_MEM && cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || (cfg->direction == DMA_MEM_TO_DEV && cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || !is_slave_direction(cfg->direction)) { return -EINVAL; } c->cfg = *cfg; return 0; Loading drivers/dma/coh901318.c +23 −5 Original line number Diff line number Diff line Loading @@ -1306,6 +1306,7 @@ struct coh901318_chan { unsigned long nbr_active_done; unsigned long busy; struct dma_slave_config config; u32 addr; u32 ctrl; Loading Loading @@ -1402,6 +1403,10 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) return container_of(chan, struct coh901318_chan, chan); } static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, struct dma_slave_config *config, enum dma_transfer_direction direction); static inline const struct coh901318_params * cohc_chan_param(struct coh901318_chan *cohc) { Loading Loading @@ -2360,6 +2365,8 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, if (lli == NULL) goto err_dma_alloc; coh901318_dma_set_runtimeconfig(chan, &cohc->config, direction); /* initiate allocated lli list */ ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, cohc->addr, Loading Loading @@ -2499,7 +2506,8 @@ static const struct burst_table burst_sizes[] = { }; static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, struct dma_slave_config *config) struct dma_slave_config *config, enum dma_transfer_direction direction) { struct coh901318_chan *cohc = to_coh901318_chan(chan); dma_addr_t addr; Loading @@ -2509,11 +2517,11 @@ static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, int i = 0; /* We only support mem to per or per to mem transfers */ if (config->direction == DMA_DEV_TO_MEM) { if (direction == DMA_DEV_TO_MEM) { addr = config->src_addr; addr_width = config->src_addr_width; maxburst = config->src_maxburst; } else if (config->direction == DMA_MEM_TO_DEV) { } else if (direction == DMA_MEM_TO_DEV) { addr = config->dst_addr; addr_width = config->dst_addr_width; maxburst = config->dst_maxburst; Loading Loading @@ -2579,6 +2587,16 @@ static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, return 0; } static int coh901318_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *config) { struct coh901318_chan *cohc = to_coh901318_chan(chan); memcpy(&cohc->config, config, sizeof(*config)); return 0; } static void coh901318_base_init(struct dma_device *dma, const int *pick_chans, struct coh901318_base *base) { Loading Loading @@ -2684,7 +2702,7 @@ static int __init coh901318_probe(struct platform_device *pdev) base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; base->dma_slave.device_tx_status = coh901318_tx_status; base->dma_slave.device_issue_pending = coh901318_issue_pending; base->dma_slave.device_config = coh901318_dma_set_runtimeconfig; base->dma_slave.device_config = coh901318_dma_slave_config; base->dma_slave.device_pause = coh901318_pause; base->dma_slave.device_resume = coh901318_resume; base->dma_slave.device_terminate_all = coh901318_terminate_all; Loading @@ -2707,7 +2725,7 @@ static int __init coh901318_probe(struct platform_device *pdev) base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; base->dma_memcpy.device_tx_status = coh901318_tx_status; base->dma_memcpy.device_issue_pending = coh901318_issue_pending; base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig; base->dma_memcpy.device_config = coh901318_dma_slave_config; base->dma_memcpy.device_pause = coh901318_pause; base->dma_memcpy.device_resume = coh901318_resume; base->dma_memcpy.device_terminate_all = coh901318_terminate_all; Loading drivers/dma/dma-jz4740.c +18 −3 Original line number Diff line number Diff line Loading @@ -113,6 +113,7 @@ struct jz4740_dma_desc { struct jz4740_dmaengine_chan { struct virt_dma_chan vchan; unsigned int id; struct dma_slave_config config; dma_addr_t fifo_addr; unsigned int transfer_shift; Loading Loading @@ -203,8 +204,9 @@ static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst) return JZ4740_DMA_TRANSFER_SIZE_32BYTE; } static int jz4740_dma_slave_config(struct dma_chan *c, struct dma_slave_config *config) static int jz4740_dma_slave_config_write(struct dma_chan *c, struct dma_slave_config *config, enum dma_transfer_direction direction) { struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c); struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan); Loading @@ -214,7 +216,7 @@ static int jz4740_dma_slave_config(struct dma_chan *c, enum jz4740_dma_flags flags; uint32_t cmd; switch (config->direction) { switch (direction) { case DMA_MEM_TO_DEV: flags = JZ4740_DMA_SRC_AUTOINC; transfer_size = jz4740_dma_maxburst(config->dst_maxburst); Loading Loading @@ -265,6 +267,15 @@ static int jz4740_dma_slave_config(struct dma_chan *c, return 0; } static int jz4740_dma_slave_config(struct dma_chan *c, struct dma_slave_config *config) { struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c); memcpy(&chan->config, config, sizeof(*config)); return 0; } static int jz4740_dma_terminate_all(struct dma_chan *c) { struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c); Loading Loading @@ -407,6 +418,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg( desc->direction = direction; desc->cyclic = false; jz4740_dma_slave_config_write(c, &chan->config, direction); return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } Loading Loading @@ -438,6 +451,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic( desc->direction = direction; desc->cyclic = true; jz4740_dma_slave_config_write(c, &chan->config, direction); return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } Loading drivers/dma/dw/core.c +0 −5 Original line number Diff line number Diff line Loading @@ -886,12 +886,7 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) */ u32 s = dw->pdata->is_idma32 ? 1 : 2; /* Check if chan will be configured for slave transfers */ if (!is_slave_direction(sconfig->direction)) return -EINVAL; memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); dwc->direction = sconfig->direction; sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0; sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0; Loading Loading
drivers/dma/at_hdmac.c +1 −1 Original line number Diff line number Diff line Loading @@ -1320,7 +1320,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, if (unlikely(!is_slave_direction(direction))) goto err_out; if (sconfig->direction == DMA_MEM_TO_DEV) if (direction == DMA_MEM_TO_DEV) reg_width = convert_buswidth(sconfig->dst_addr_width); else reg_width = convert_buswidth(sconfig->src_addr_width); Loading
drivers/dma/bcm2835-dma.c +0 −8 Original line number Diff line number Diff line Loading @@ -778,14 +778,6 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan, { struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); if ((cfg->direction == DMA_DEV_TO_MEM && cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || (cfg->direction == DMA_MEM_TO_DEV && cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || !is_slave_direction(cfg->direction)) { return -EINVAL; } c->cfg = *cfg; return 0; Loading
drivers/dma/coh901318.c +23 −5 Original line number Diff line number Diff line Loading @@ -1306,6 +1306,7 @@ struct coh901318_chan { unsigned long nbr_active_done; unsigned long busy; struct dma_slave_config config; u32 addr; u32 ctrl; Loading Loading @@ -1402,6 +1403,10 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) return container_of(chan, struct coh901318_chan, chan); } static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, struct dma_slave_config *config, enum dma_transfer_direction direction); static inline const struct coh901318_params * cohc_chan_param(struct coh901318_chan *cohc) { Loading Loading @@ -2360,6 +2365,8 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, if (lli == NULL) goto err_dma_alloc; coh901318_dma_set_runtimeconfig(chan, &cohc->config, direction); /* initiate allocated lli list */ ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, cohc->addr, Loading Loading @@ -2499,7 +2506,8 @@ static const struct burst_table burst_sizes[] = { }; static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, struct dma_slave_config *config) struct dma_slave_config *config, enum dma_transfer_direction direction) { struct coh901318_chan *cohc = to_coh901318_chan(chan); dma_addr_t addr; Loading @@ -2509,11 +2517,11 @@ static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, int i = 0; /* We only support mem to per or per to mem transfers */ if (config->direction == DMA_DEV_TO_MEM) { if (direction == DMA_DEV_TO_MEM) { addr = config->src_addr; addr_width = config->src_addr_width; maxburst = config->src_maxburst; } else if (config->direction == DMA_MEM_TO_DEV) { } else if (direction == DMA_MEM_TO_DEV) { addr = config->dst_addr; addr_width = config->dst_addr_width; maxburst = config->dst_maxburst; Loading Loading @@ -2579,6 +2587,16 @@ static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, return 0; } static int coh901318_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *config) { struct coh901318_chan *cohc = to_coh901318_chan(chan); memcpy(&cohc->config, config, sizeof(*config)); return 0; } static void coh901318_base_init(struct dma_device *dma, const int *pick_chans, struct coh901318_base *base) { Loading Loading @@ -2684,7 +2702,7 @@ static int __init coh901318_probe(struct platform_device *pdev) base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; base->dma_slave.device_tx_status = coh901318_tx_status; base->dma_slave.device_issue_pending = coh901318_issue_pending; base->dma_slave.device_config = coh901318_dma_set_runtimeconfig; base->dma_slave.device_config = coh901318_dma_slave_config; base->dma_slave.device_pause = coh901318_pause; base->dma_slave.device_resume = coh901318_resume; base->dma_slave.device_terminate_all = coh901318_terminate_all; Loading @@ -2707,7 +2725,7 @@ static int __init coh901318_probe(struct platform_device *pdev) base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; base->dma_memcpy.device_tx_status = coh901318_tx_status; base->dma_memcpy.device_issue_pending = coh901318_issue_pending; base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig; base->dma_memcpy.device_config = coh901318_dma_slave_config; base->dma_memcpy.device_pause = coh901318_pause; base->dma_memcpy.device_resume = coh901318_resume; base->dma_memcpy.device_terminate_all = coh901318_terminate_all; Loading
drivers/dma/dma-jz4740.c +18 −3 Original line number Diff line number Diff line Loading @@ -113,6 +113,7 @@ struct jz4740_dma_desc { struct jz4740_dmaengine_chan { struct virt_dma_chan vchan; unsigned int id; struct dma_slave_config config; dma_addr_t fifo_addr; unsigned int transfer_shift; Loading Loading @@ -203,8 +204,9 @@ static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst) return JZ4740_DMA_TRANSFER_SIZE_32BYTE; } static int jz4740_dma_slave_config(struct dma_chan *c, struct dma_slave_config *config) static int jz4740_dma_slave_config_write(struct dma_chan *c, struct dma_slave_config *config, enum dma_transfer_direction direction) { struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c); struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan); Loading @@ -214,7 +216,7 @@ static int jz4740_dma_slave_config(struct dma_chan *c, enum jz4740_dma_flags flags; uint32_t cmd; switch (config->direction) { switch (direction) { case DMA_MEM_TO_DEV: flags = JZ4740_DMA_SRC_AUTOINC; transfer_size = jz4740_dma_maxburst(config->dst_maxburst); Loading Loading @@ -265,6 +267,15 @@ static int jz4740_dma_slave_config(struct dma_chan *c, return 0; } static int jz4740_dma_slave_config(struct dma_chan *c, struct dma_slave_config *config) { struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c); memcpy(&chan->config, config, sizeof(*config)); return 0; } static int jz4740_dma_terminate_all(struct dma_chan *c) { struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c); Loading Loading @@ -407,6 +418,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg( desc->direction = direction; desc->cyclic = false; jz4740_dma_slave_config_write(c, &chan->config, direction); return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } Loading Loading @@ -438,6 +451,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic( desc->direction = direction; desc->cyclic = true; jz4740_dma_slave_config_write(c, &chan->config, direction); return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } Loading
drivers/dma/dw/core.c +0 −5 Original line number Diff line number Diff line Loading @@ -886,12 +886,7 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) */ u32 s = dw->pdata->is_idma32 ? 1 : 2; /* Check if chan will be configured for slave transfers */ if (!is_slave_direction(sconfig->direction)) return -EINVAL; memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); dwc->direction = sconfig->direction; sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0; sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0; Loading