Commit edabcf71 authored by Rex-BC Chen's avatar Rex-BC Chen Committed by Stephen Boyd
Browse files

clk: mediatek: reset: Fix written reset bit offset 



Original assert/deassert bit is BIT(0), but it's more resonable to modify
them to BIT(id % 32) which is based on id.

This patch will not influence any previous driver because the reset is
only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.

Fixes: 64ebb57a ("clk: reset: Modify reset-controller driver")
Signed-off-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-3-rex-bc.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b348c26c

drivers/clk/mediatek/reset.c

+2 −2
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, 
	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);

	unsigned int reg = data->regofs + ((id / 32) << 4);



	return regmap_write(data->regmap, reg, 1);

	return regmap_write(data->regmap, reg, BIT(id % 32));

}



static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
@@ -27,7 +27,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, 
	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);

	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;



	return regmap_write(data->regmap, reg, 1);

	return regmap_write(data->regmap, reg, BIT(id % 32));

}



static int mtk_reset_assert(struct reset_controller_dev *rcdev,