Commit eda80b24 authored by Daniel Golle's avatar Daniel Golle Committed by David S. Miller
Browse files

net: ethernet: mtk_eth_soc: fix return values and refactor MDIO ops 



Instead of returning -1 (-EPERM) when MDIO bus is stuck busy
while writing or 0xffff if it happens while reading, return the
appropriate -ETIMEDOUT. Also fix return type to int instead of u32.
Refactor functions to use bitfield helpers instead of having various
masking and shifting constants in the code, which also results in the
register definitions in the header file being more obviously related
to what is stated in the MediaTek's Reference Manual.

Fixes: 656e7052 ("net-next: mediatek: add support for MT7623 ethernet")
Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ffd32ea6

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+30 −23
Original line number Diff line number Diff line
@@ -91,46 +91,53 @@ static int mtk_mdio_busy_wait(struct mtk_eth *eth) 
	}



	dev_err(eth->dev, "mdio: MDIO timeout\n");

	return -1;

	return -ETIMEDOUT;

}



static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,

			   u32 phy_register, u32 write_data)

static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,

			   u32 write_data)

{

	if (mtk_mdio_busy_wait(eth))

		return -1;

	int ret;



	write_data &= 0xffff;

	ret = mtk_mdio_busy_wait(eth);

	if (ret < 0)

		return ret;



	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |

		(phy_register << PHY_IAC_REG_SHIFT) |

		(phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,

	mtk_w32(eth, PHY_IAC_ACCESS |

		     PHY_IAC_START_C22 |

		     PHY_IAC_CMD_WRITE |

		     PHY_IAC_REG(phy_reg) |

		     PHY_IAC_ADDR(phy_addr) |

		     PHY_IAC_DATA(write_data),

		MTK_PHY_IAC);



	if (mtk_mdio_busy_wait(eth))

		return -1;

	ret = mtk_mdio_busy_wait(eth);

	if (ret < 0)

		return ret;



	return 0;

}



static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)

static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)

{

	u32 d;

	int ret;



	if (mtk_mdio_busy_wait(eth))

		return 0xffff;

	ret = mtk_mdio_busy_wait(eth);

	if (ret < 0)

		return ret;



	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |

		(phy_reg << PHY_IAC_REG_SHIFT) |

		(phy_addr << PHY_IAC_ADDR_SHIFT),

	mtk_w32(eth, PHY_IAC_ACCESS |

		     PHY_IAC_START_C22 |

		     PHY_IAC_CMD_C22_READ |

		     PHY_IAC_REG(phy_reg) |

		     PHY_IAC_ADDR(phy_addr),

		MTK_PHY_IAC);



	if (mtk_mdio_busy_wait(eth))

		return 0xffff;



	d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;

	ret = mtk_mdio_busy_wait(eth);

	if (ret < 0)

		return ret;



	return d;

	return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;

}



static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+11 −5
Original line number Diff line number Diff line
@@ -341,11 +341,17 @@ 
/* PHY Indirect Access Control registers */

#define MTK_PHY_IAC		0x10004

#define PHY_IAC_ACCESS		BIT(31)

#define PHY_IAC_READ		BIT(19)

#define PHY_IAC_WRITE		BIT(18)

#define PHY_IAC_START		BIT(16)

#define PHY_IAC_ADDR_SHIFT	20

#define PHY_IAC_REG_SHIFT	25

#define PHY_IAC_REG_MASK	GENMASK(29, 25)

#define PHY_IAC_REG(x)		FIELD_PREP(PHY_IAC_REG_MASK, (x))

#define PHY_IAC_ADDR_MASK	GENMASK(24, 20)

#define PHY_IAC_ADDR(x)		FIELD_PREP(PHY_IAC_ADDR_MASK, (x))

#define PHY_IAC_CMD_MASK	GENMASK(19, 18)

#define PHY_IAC_CMD_WRITE	FIELD_PREP(PHY_IAC_CMD_MASK, 1)

#define PHY_IAC_CMD_C22_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 2)

#define PHY_IAC_START_MASK	GENMASK(17, 16)

#define PHY_IAC_START_C22	FIELD_PREP(PHY_IAC_START_MASK, 1)

#define PHY_IAC_DATA_MASK	GENMASK(15, 0)

#define PHY_IAC_DATA(x)		FIELD_PREP(PHY_IAC_DATA_MASK, (x))

#define PHY_IAC_TIMEOUT		HZ



#define MTK_MAC_MISC		0x1000c