Commit eda2171d authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/cpufeature' into for-next/core 

Additional CPU sanity checks for MTE and preparatory changes for systems
where not all of the CPUs support 32-bit EL0.

* for-next/cpufeature:
  arm64: Restrict undef hook for cpufeature registers
  arm64: Kill 32-bit applications scheduled on 64-bit-only CPUs
  KVM: arm64: Kill 32-bit vCPUs on systems with mismatched EL0 support
  arm64: Allow mismatched 32-bit EL0 support
  arm64: cpuinfo: Split AArch32 registers out into a separate struct
  arm64: Check if GMID_EL1.BS is the same on all CPUs
  arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
parents 5ceb0455 cf292e93

arch/arm64/include/asm/cpu.h

+25 −20
Original line number Original line Diff line number Diff line
@@ -12,26 +12,7 @@ 
/*

/*

 * Records attributes of an individual CPU.

 * Records attributes of an individual CPU.

 */

 */

struct cpuinfo_arm64 {

struct cpuinfo_32bit {

	struct cpu	cpu;

	struct kobject	kobj;

	u32		reg_ctr;

	u32		reg_cntfrq;

	u32		reg_dczid;

	u32		reg_midr;

	u32		reg_revidr;



	u64		reg_id_aa64dfr0;

	u64		reg_id_aa64dfr1;

	u64		reg_id_aa64isar0;

	u64		reg_id_aa64isar1;

	u64		reg_id_aa64mmfr0;

	u64		reg_id_aa64mmfr1;

	u64		reg_id_aa64mmfr2;

	u64		reg_id_aa64pfr0;

	u64		reg_id_aa64pfr1;

	u64		reg_id_aa64zfr0;



	u32		reg_id_dfr0;

	u32		reg_id_dfr0;

	u32		reg_id_dfr1;

	u32		reg_id_dfr1;

	u32		reg_id_isar0;

	u32		reg_id_isar0;
@@ -54,6 +35,30 @@ struct cpuinfo_arm64 { 
	u32		reg_mvfr0;

	u32		reg_mvfr0;

	u32		reg_mvfr1;

	u32		reg_mvfr1;

	u32		reg_mvfr2;

	u32		reg_mvfr2;

};



struct cpuinfo_arm64 {

	struct cpu	cpu;

	struct kobject	kobj;

	u64		reg_ctr;

	u64		reg_cntfrq;

	u64		reg_dczid;

	u64		reg_midr;

	u64		reg_revidr;

	u64		reg_gmid;



	u64		reg_id_aa64dfr0;

	u64		reg_id_aa64dfr1;

	u64		reg_id_aa64isar0;

	u64		reg_id_aa64isar1;

	u64		reg_id_aa64mmfr0;

	u64		reg_id_aa64mmfr1;

	u64		reg_id_aa64mmfr2;

	u64		reg_id_aa64pfr0;

	u64		reg_id_aa64pfr1;

	u64		reg_id_aa64zfr0;



	struct cpuinfo_32bit	aarch32;





	/* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */

	/* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */

	u64		reg_zcr;

	u64		reg_zcr;

arch/arm64/include/asm/cpufeature.h

+14 −1
Original line number Original line Diff line number Diff line
@@ -619,6 +619,13 @@ static inline bool id_aa64pfr0_sve(u64 pfr0) 
	return val > 0;

	return val > 0;

}

}





static inline bool id_aa64pfr1_mte(u64 pfr1)

{

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_MTE_SHIFT);



	return val >= ID_AA64PFR1_MTE;

}



void __init setup_cpu_features(void);

void __init setup_cpu_features(void);

void check_local_cpu_capabilities(void);

void check_local_cpu_capabilities(void);
@@ -630,9 +637,15 @@ static inline bool cpu_supports_mixed_endian_el0(void) 
	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));

	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));

}

}





const struct cpumask *system_32bit_el0_cpumask(void);

DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);



static inline bool system_supports_32bit_el0(void)

static inline bool system_supports_32bit_el0(void)

{

{

	return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);

	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);



	return static_branch_unlikely(&arm64_mismatched_32bit_el0) ||

	       id_aa64pfr0_32bit_el0(pfr0);

}

}





static inline bool system_supports_4kb_granule(void)

static inline bool system_supports_4kb_granule(void)

arch/arm64/kernel/cpufeature.c

+161 −48
Original line number Original line Diff line number Diff line
@@ -107,6 +107,24 @@ DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 
bool arm64_use_ng_mappings = false;

bool arm64_use_ng_mappings = false;

EXPORT_SYMBOL(arm64_use_ng_mappings);

EXPORT_SYMBOL(arm64_use_ng_mappings);





/*

 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs

 * support it?

 */

static bool __read_mostly allow_mismatched_32bit_el0;



/*

 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have

 * seen at least one CPU capable of 32-bit EL0.

 */

DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);



/*

 * Mask of CPUs supporting 32-bit EL0.

 * Only valid if arm64_mismatched_32bit_el0 is enabled.

 */

static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;



/*

/*

 * Flag to indicate if we have computed the system wide

 * Flag to indicate if we have computed the system wide

 * capabilities based on the boot time active CPUs. This

 * capabilities based on the boot time active CPUs. This
@@ -400,6 +418,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = { 
	ARM64_FTR_END,

	ARM64_FTR_END,

};

};





static const struct arm64_ftr_bits ftr_gmid[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar0[] = {

static const struct arm64_ftr_bits ftr_id_isar0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
@@ -617,6 +640,9 @@ static const struct __ftr_reg_entry { 
	/* Op1 = 0, CRn = 1, CRm = 2 */

	/* Op1 = 0, CRn = 1, CRm = 2 */

	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),

	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),





	/* Op1 = 1, CRn = 0, CRm = 0 */

	ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),



	/* Op1 = 3, CRn = 0, CRm = 0 */

	/* Op1 = 3, CRn = 0, CRm = 0 */

	{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },

	{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },

	ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),

	ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
@@ -767,7 +793,7 @@ static void __init sort_ftr_regs(void) 
 * Any bits that are not covered by an arm64_ftr_bits entry are considered

 * Any bits that are not covered by an arm64_ftr_bits entry are considered

 * RES0 for the system-wide value, and must strictly match.

 * RES0 for the system-wide value, and must strictly match.

 */

 */

static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)

static void init_cpu_ftr_reg(u32 sys_reg, u64 new)

{

{

	u64 val = 0;

	u64 val = 0;

	u64 strict_mask = ~0x0ULL;

	u64 strict_mask = ~0x0ULL;
@@ -863,26 +889,8 @@ static void __init init_cpu_hwcaps_indirect_list(void) 




static void __init setup_boot_cpu_capabilities(void);

static void __init setup_boot_cpu_capabilities(void);





void __init init_cpu_features(struct cpuinfo_arm64 *info)

static void init_32bit_cpu_features(struct cpuinfo_32bit *info)

{

{

	/* Before we start using the tables, make sure it is sorted */

	sort_ftr_regs();



	init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);

	init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);

	init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);

	init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);

	init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);

	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);

	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);

	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);



	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {

	init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);

	init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);

	init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);

	init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);

	init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);

	init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
@@ -906,11 +914,36 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
	init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);

	init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);

}

}





void __init init_cpu_features(struct cpuinfo_arm64 *info)

{

	/* Before we start using the tables, make sure it is sorted */

	sort_ftr_regs();



	init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);

	init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);

	init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);

	init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);

	init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);

	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);

	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);

	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);



	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))

		init_32bit_cpu_features(&info->aarch32);



	if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {

	if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {

		init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);

		init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);

		sve_init_vq_map();

		sve_init_vq_map();

	}

	}





	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))

		init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);



	/*

	/*

	 * Initialize the indirect array of CPU hwcaps capabilities pointers

	 * Initialize the indirect array of CPU hwcaps capabilities pointers

	 * before we handle the boot CPU below.

	 * before we handle the boot CPU below.
@@ -975,20 +1008,28 @@ static void relax_cpu_ftr_reg(u32 sys_id, int field) 
	WARN_ON(!ftrp->width);

	WARN_ON(!ftrp->width);

}

}





static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,

static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,

					 struct cpuinfo_arm64 *boot)

					 struct cpuinfo_arm64 *boot)

{

	static bool boot_cpu_32bit_regs_overridden = false;



	if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)

		return;



	if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))

		return;



	boot->aarch32 = info->aarch32;

	init_32bit_cpu_features(&boot->aarch32);

	boot_cpu_32bit_regs_overridden = true;

}



static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,

				     struct cpuinfo_32bit *boot)

{

{

	int taint = 0;

	int taint = 0;

	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);

	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);





	/*

	 * If we don't have AArch32 at all then skip the checks entirely

	 * as the register values may be UNKNOWN and we're not going to be

	 * using them for anything.

	 */

	if (!id_aa64pfr0_32bit_el0(pfr0))

		return taint;



	/*

	/*

	 * If we don't have AArch32 at EL1, then relax the strictness of

	 * If we don't have AArch32 at EL1, then relax the strictness of

	 * EL1-dependent register fields to avoid spurious sanity check fails.

	 * EL1-dependent register fields to avoid spurious sanity check fails.
@@ -1135,10 +1176,29 @@ void update_cpu_features(int cpu, 
	}

	}





	/*

	/*

	 * The kernel uses the LDGM/STGM instructions and the number of tags

	 * they read/write depends on the GMID_EL1.BS field. Check that the

	 * value is the same on all CPUs.

	 */

	if (IS_ENABLED(CONFIG_ARM64_MTE) &&

	    id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {

		taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,

					      info->reg_gmid, boot->reg_gmid);

	}



	/*

	 * If we don't have AArch32 at all then skip the checks entirely

	 * as the register values may be UNKNOWN and we're not going to be

	 * using them for anything.

	 *

	 * This relies on a sanitised view of the AArch64 ID registers

	 * This relies on a sanitised view of the AArch64 ID registers

	 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.

	 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.

	 */

	 */

	taint |= update_32bit_cpu_features(cpu, info, boot);

	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {

		lazy_init_32bit_cpu_features(info, boot);

		taint |= update_32bit_cpu_features(cpu, &info->aarch32,

						   &boot->aarch32);

	}





	/*

	/*

	 * Mismatched CPU features are a recipe for disaster. Don't even

	 * Mismatched CPU features are a recipe for disaster. Don't even
@@ -1248,6 +1308,28 @@ has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 
	return feature_matches(val, entry);

	return feature_matches(val, entry);

}

}





const struct cpumask *system_32bit_el0_cpumask(void)

{

	if (!system_supports_32bit_el0())

		return cpu_none_mask;



	if (static_branch_unlikely(&arm64_mismatched_32bit_el0))

		return cpu_32bit_el0_mask;



	return cpu_possible_mask;

}



static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)

{

	if (!has_cpuid_feature(entry, scope))

		return allow_mismatched_32bit_el0;



	if (scope == SCOPE_SYSTEM)

		pr_info("detected: 32-bit EL0 Support\n");



	return true;

}



static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)

static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)

{

{

	bool has_sre;

	bool has_sre;
@@ -1866,10 +1948,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.cpu_enable = cpu_copy_el2regs,

		.cpu_enable = cpu_copy_el2regs,

	},

	},

	{

	{

		.desc = "32-bit EL0 Support",

		.capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,

		.capability = ARM64_HAS_32BIT_EL0,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.matches = has_32bit_el0,

		.sys_reg = SYS_ID_AA64PFR0_EL1,

		.sys_reg = SYS_ID_AA64PFR0_EL1,

		.sign = FTR_UNSIGNED,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR0_EL0_SHIFT,

		.field_pos = ID_AA64PFR0_EL0_SHIFT,
@@ -2378,7 +2459,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 
	{},

	{},

};

};





static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)

static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)

{

{

	switch (cap->hwcap_type) {

	switch (cap->hwcap_type) {

	case CAP_HWCAP:

	case CAP_HWCAP:
@@ -2423,7 +2504,7 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 
	return rc;

	return rc;

}

}





static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)

static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)

{

{

	/* We support emulation of accesses to CPU ID feature registers */

	/* We support emulation of accesses to CPU ID feature registers */

	cpu_set_named_feature(CPUID);

	cpu_set_named_feature(CPUID);
@@ -2598,7 +2679,7 @@ static void check_early_cpu_features(void) 
}

}





static void

static void

verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)

__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)

{

{





	for (; caps->matches; caps++)

	for (; caps->matches; caps++)
@@ -2609,6 +2690,14 @@ verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 
		}

		}

}

}





static void verify_local_elf_hwcaps(void)

{

	__verify_local_elf_hwcaps(arm64_elf_hwcaps);



	if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))

		__verify_local_elf_hwcaps(compat_elf_hwcaps);

}



static void verify_sve_features(void)

static void verify_sve_features(void)

{

{

	u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);

	u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
@@ -2673,11 +2762,7 @@ static void verify_local_cpu_capabilities(void) 
	 * on all secondary CPUs.

	 * on all secondary CPUs.

	 */

	 */

	verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);

	verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);



	verify_local_elf_hwcaps();

	verify_local_elf_hwcaps(arm64_elf_hwcaps);



	if (system_supports_32bit_el0())

		verify_local_elf_hwcaps(compat_elf_hwcaps);





	if (system_supports_sve())

	if (system_supports_sve())

		verify_sve_features();

		verify_sve_features();
@@ -2812,6 +2897,34 @@ void __init setup_cpu_features(void) 
			ARCH_DMA_MINALIGN);

			ARCH_DMA_MINALIGN);

}

}





static int enable_mismatched_32bit_el0(unsigned int cpu)

{

	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);

	bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);



	if (cpu_32bit) {

		cpumask_set_cpu(cpu, cpu_32bit_el0_mask);

		static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);

		setup_elf_hwcaps(compat_elf_hwcaps);

	}



	return 0;

}



static int __init init_32bit_el0_mask(void)

{

	if (!allow_mismatched_32bit_el0)

		return 0;



	if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))

		return -ENOMEM;



	return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,

				 "arm64/mismatched_32bit_el0:online",

				 enable_mismatched_32bit_el0, NULL);

}

subsys_initcall_sync(init_32bit_el0_mask);



static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)

static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)

{

{

	cpu_replace_ttbr1(lm_alias(swapper_pg_dir));

	cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
@@ -2905,8 +3018,8 @@ static int emulate_mrs(struct pt_regs *regs, u32 insn) 
}

}





static struct undef_hook mrs_hook = {

static struct undef_hook mrs_hook = {

	.instr_mask = 0xfff00000,

	.instr_mask = 0xffff0000,

	.instr_val  = 0xd5300000,

	.instr_val  = 0xd5380000,

	.pstate_mask = PSR_AA32_MODE_MASK,

	.pstate_mask = PSR_AA32_MODE_MASK,

	.pstate_val = PSR_MODE_EL0t,

	.pstate_val = PSR_MODE_EL0t,

	.fn = emulate_mrs,

	.fn = emulate_mrs,

arch/arm64/kernel/cpuinfo.c

+32 −26
Original line number Original line Diff line number Diff line
@@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = { 
		struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);		\

		struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);		\

										\

										\

		if (info->reg_midr)						\

		if (info->reg_midr)						\

			return sprintf(buf, "0x%016x\n", info->reg_##_field);	\

			return sprintf(buf, "0x%016llx\n", info->reg_##_field);	\

		else								\

		else								\

			return 0;						\

			return 0;						\

	}									\

	}									\
@@ -344,6 +344,32 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 
	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);

	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);

}

}





static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)

{

	info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);

	info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);

	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);

	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);

	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);

	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);

	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);

	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);

	info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);

	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);

	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);

	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);

	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);

	info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);

	info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);

	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);

	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);

	info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);



	info->reg_mvfr0 = read_cpuid(MVFR0_EL1);

	info->reg_mvfr1 = read_cpuid(MVFR1_EL1);

	info->reg_mvfr2 = read_cpuid(MVFR2_EL1);

}



static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)

static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)

{

{

	info->reg_cntfrq = arch_timer_get_cntfrq();

	info->reg_cntfrq = arch_timer_get_cntfrq();
@@ -371,31 +397,11 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);

	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);

	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);

	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);





	/* Update the 32bit ID registers only if AArch32 is implemented */

	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))

	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {

		info->reg_gmid = read_cpuid(GMID_EL1);

		info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);

		info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);

		info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);

		info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);

		info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);

		info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);

		info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);

		info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);

		info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);

		info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);

		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);

		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);

		info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);

		info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);

		info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);

		info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);

		info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);

		info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);





		info->reg_mvfr0 = read_cpuid(MVFR0_EL1);

	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))

		info->reg_mvfr1 = read_cpuid(MVFR1_EL1);

		__cpuinfo_store_cpu_32bit(&info->aarch32);

		info->reg_mvfr2 = read_cpuid(MVFR2_EL1);

	}





	if (IS_ENABLED(CONFIG_ARM64_SVE) &&

	if (IS_ENABLED(CONFIG_ARM64_SVE) &&

	    id_aa64pfr0_sve(info->reg_id_aa64pfr0))

	    id_aa64pfr0_sve(info->reg_id_aa64pfr0))

arch/arm64/kernel/process.c

+18 −1
Original line number Original line Diff line number Diff line
@@ -532,6 +532,15 @@ static void erratum_1418040_thread_switch(struct task_struct *prev, 
	write_sysreg(val, cntkctl_el1);

	write_sysreg(val, cntkctl_el1);

}

}





static void compat_thread_switch(struct task_struct *next)

{

	if (!is_compat_thread(task_thread_info(next)))

		return;



	if (static_branch_unlikely(&arm64_mismatched_32bit_el0))

		set_tsk_thread_flag(next, TIF_NOTIFY_RESUME);

}



static void update_sctlr_el1(u64 sctlr)

static void update_sctlr_el1(u64 sctlr)

{

{

	/*

	/*
@@ -573,6 +582,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, 
	ssbs_thread_switch(next);

	ssbs_thread_switch(next);

	erratum_1418040_thread_switch(prev, next);

	erratum_1418040_thread_switch(prev, next);

	ptrauth_thread_switch_user(next);

	ptrauth_thread_switch_user(next);

	compat_thread_switch(next);





	/*

	/*

	 * Complete any pending TLB or cache maintenance on this CPU in case

	 * Complete any pending TLB or cache maintenance on this CPU in case
@@ -638,8 +648,15 @@ unsigned long arch_align_stack(unsigned long sp) 
 */

 */

void arch_setup_new_exec(void)

void arch_setup_new_exec(void)

{

{

	current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;

	unsigned long mmflags = 0;



	if (is_compat_task()) {

		mmflags = MMCF_AARCH32;

		if (static_branch_unlikely(&arm64_mismatched_32bit_el0))

			set_tsk_thread_flag(current, TIF_NOTIFY_RESUME);

	}





	current->mm->context.flags = mmflags;

	ptrauth_thread_init_user();

	ptrauth_thread_init_user();

	mte_thread_init_user();

	mte_thread_init_user();