Commit ed941f65 authored by Michael Walle's avatar Michael Walle Committed by David S. Miller
Browse files

dt-bindings: net: convert mscc-miim to YAML format 



Convert the mscc-miim device tree binding to the new YAML format.

The original binding don't mention if the interrupt property is optional
or not. But on the SparX-5 SoC, for example, the interrupt property isn't
used, thus in the new binding that property is optional. FWIW the driver
doesn't use interrupts at all.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1ee375d7

Documentation/devicetree/bindings/net/mscc,miim.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/mscc,miim.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microsemi MII Management Controller (MIIM)



maintainers:

  - Alexandre Belloni <alexandre.belloni@bootlin.com>



allOf:

  - $ref: "mdio.yaml#"



properties:

  compatible:

    enum:

      - mscc,ocelot-miim

      - microchip,lan966x-miim



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



  reg:

    items:

      - description: base address

      - description: associated reset register for internal PHYs

    minItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"



unevaluatedProperties: false



examples:

  - |

    mdio@107009c {

      compatible = "mscc,ocelot-miim";

      reg = <0x107009c 0x36>, <0x10700f0 0x8>;

      interrupts = <14>;

      #address-cells = <1>;

      #size-cells = <0>;



      phy0: ethernet-phy@0 {

        reg = <0>;

      };

    };

Documentation/devicetree/bindings/net/mscc-miim.txt

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Microsemi MII Management Controller (MIIM) / MDIO

=================================================



Properties:

- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim"

- reg: The base address of the MDIO bus controller register bank. Optionally, a

  second register bank can be defined if there is an associated reset register

  for internal PHYs

- #address-cells: Must be <1>.

- #size-cells: Must be <0>.  MDIO addresses have no size component.

- interrupts: interrupt specifier (refer to the interrupt binding)



Typically an MDIO bus might have several children.



Example:

	mdio@107009c {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "mscc,ocelot-miim";

		reg = <0x107009c 0x36>, <0x10700f0 0x8>;

		interrupts = <14>;



		phy0: ethernet-phy@0 {

			reg = <0>;

		};

	};