Commit ed72aa21 authored by Guchun Chen's avatar Guchun Chen Committed by Alex Deucher
Browse files

drm/amdgpu: replace DRM prefix with PCI device info for GFX RAS 



Prefix RAS message printing in GFX IP with PCI device info,
which assists the debug in multiple GPU case.

Signed-off-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d32709da

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+27 −20
Original line number Diff line number Diff line
@@ -6396,15 +6396,15 @@ static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 


		sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

				 vml2_mems[i], sec_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"SEC %d\n", i, vml2_mems[i], sec_count);

			err_data->ce_count += sec_count;

		}



		ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

				 vml2_mems[i], ded_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"DED %d\n", i, vml2_mems[i], ded_count);

			err_data->ue_count += ded_count;

		}

	}
@@ -6416,16 +6416,16 @@ static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 
		sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,

						SEC_COUNT);

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

				 vml2_walker_mems[i], sec_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"SEC %d\n", i, vml2_walker_mems[i], sec_count);

			err_data->ce_count += sec_count;

		}



		ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,

						DED_COUNT);

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

				 vml2_walker_mems[i], ded_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"DED %d\n", i, vml2_walker_mems[i], ded_count);

			err_data->ue_count += ded_count;

		}

	}
@@ -6436,8 +6436,9 @@ static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 


		sec_count = (data & 0x00006000L) >> 0xd;

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

				 atc_l2_cache_2m_mems[i], sec_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"SEC %d\n", i, atc_l2_cache_2m_mems[i],

				sec_count);

			err_data->ce_count += sec_count;

		}

	}
@@ -6448,15 +6449,17 @@ static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 


		sec_count = (data & 0x00006000L) >> 0xd;

		if (sec_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,

				 atc_l2_cache_4k_mems[i], sec_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"SEC %d\n", i, atc_l2_cache_4k_mems[i],

				sec_count);

			err_data->ce_count += sec_count;

		}



		ded_count = (data & 0x00018000L) >> 0xf;

		if (ded_count) {

			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,

				 atc_l2_cache_4k_mems[i], ded_count);

			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "

				"DED %d\n", i, atc_l2_cache_4k_mems[i],

				ded_count);

			err_data->ue_count += ded_count;

		}

	}
@@ -6469,7 +6472,8 @@ static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 
	return 0;

}



static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg,

static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev,

	const struct soc15_reg_entry *reg,

	uint32_t se_id, uint32_t inst_id, uint32_t value,

	uint32_t *sec_count, uint32_t *ded_count)

{
@@ -6486,7 +6490,8 @@ static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg, 
				gfx_v9_0_ras_fields[i].sec_count_mask) >>

				gfx_v9_0_ras_fields[i].sec_count_shift;

		if (sec_cnt) {

			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",

			dev_info(adev->dev, "GFX SubBlock %s, "

				"Instance[%d][%d], SEC %d\n",

				gfx_v9_0_ras_fields[i].name,

				se_id, inst_id,

				sec_cnt);
@@ -6497,7 +6502,8 @@ static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg, 
				gfx_v9_0_ras_fields[i].ded_count_mask) >>

				gfx_v9_0_ras_fields[i].ded_count_shift;

		if (ded_cnt) {

			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",

			dev_info(adev->dev, "GFX SubBlock %s, "

				"Instance[%d][%d], DED %d\n",

				gfx_v9_0_ras_fields[i].name,

				se_id, inst_id,

				ded_cnt);
@@ -6586,7 +6592,8 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 
				reg_value =

					RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));

				if (reg_value)

					gfx_v9_0_ras_error_count(&gfx_v9_0_edc_counter_regs[i],

					gfx_v9_0_ras_error_count(adev,

						&gfx_v9_0_edc_counter_regs[i],

						j, k, reg_value,

						&sec_count, &ded_count);

			}