Commit ed6b25aa authored by Umesh Nerlige Ramappa's avatar Umesh Nerlige Ramappa Committed by John Harrison
Browse files

drm/i915/perf: Add Wa_1508761755:dg2 



Disable Clock gating in EU when gathering the events so that EU events
are not lost.

v2: Fix checkpatch issues
v3: User MCR helpers to write to MC reg
v4: Indent correctly (checkpatch)

Signed-off-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-12-umesh.nerlige.ramappa@intel.com
parent 90981da6

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -1162,6 +1162,7 @@ 
#define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)

#define   GEN12_ENABLE_LARGE_GRF_MODE		REG_BIT(12)

#define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)

#define   GEN12_DISABLE_DOP_GATING              REG_BIT(0)



#define RT_CTRL					MCR_REG(0xe530)

#define   DIS_NULL_QUERY			REG_BIT(10)

drivers/gpu/drm/i915/i915_perf.c

+24 −0
Original line number Diff line number Diff line
@@ -204,6 +204,7 @@ 
#include "gt/intel_gpu_commands.h"

#include "gt/intel_gt.h"

#include "gt/intel_gt_clock_utils.h"

#include "gt/intel_gt_mcr.h"

#include "gt/intel_gt_regs.h"

#include "gt/intel_lrc.h"

#include "gt/intel_lrc_reg.h"
@@ -2775,6 +2776,18 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, 
	u32 sqcnt1;

	int ret;



	/*

	 * Wa_1508761755:xehpsdv, dg2

	 * EU NOA signals behave incorrectly if EU clock gating is enabled.

	 * Disable thread stall DOP gating and EU DOP gating.

	 */

	if (IS_XEHPSDV(i915) || IS_DG2(i915)) {

		intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,

					     _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));

		intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,

				   _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));

	}



	intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,

			   /* Disable clk ratio reports, like previous Gens. */

			   _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
@@ -2853,6 +2866,17 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream) 
	struct drm_i915_private *i915 = stream->perf->i915;

	u32 sqcnt1;



	/*

	 * Wa_1508761755:xehpsdv, dg2

	 * Enable thread stall DOP gating and EU DOP gating.

	 */

	if (IS_XEHPSDV(i915) || IS_DG2(i915)) {

		intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,

					     _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));

		intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,

				   _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));

	}



	/* Reset all contexts' slices/subslices configurations. */

	gen12_configure_all_contexts(stream, NULL, NULL);