Unverified Commit ed3dd346 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!807 Backport 5.10.153 LTS 

Merge Pull Request from: @sanglipeng 
 
Backport 5.10.153 LTS patches from upstream.

Conflicts:

Already merged(3):
935a8b620210 mm/memory: add non-anonymous page check in the copy_present_page()
568e3812b177 mm,hugetlb: take hugetlb_lock before decrementing h->resv_huge_pages
  (Already merged mainline commit 12df140f mm,hugetlb: take hugetlb_lock before decrementing h->resv_huge_pages)
d523384766fd scsi: sd: Revert "scsi: sd: Remove a local variable"
  (Already merged commit 7d7fe3e4 scsi: sd: Revert "scsi: sd: Remove a local variable") 

Context confilict(1):  
3b250824b6d3 xhci: Add quirk to reset host back to default state at shutdown
        
Rejected(4):
ce605b68db53 net: hinic: fix incorrect assignment issue in hinic_set_interrupt_cfg()
  (The involved file drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c is already deleted
    by the commit f1168d29 net/hinic: Update Hardware Abstract Layer)
bb01910763f9 net: hinic: fix memory leak when reading function table
  (The involved file drivers/net/ethernet/huawei/hinic/hinic_debugfs.c is already deleted
    by the commit f1168d29 net/hinic: Update Hardware Abstract Layer)
6603843c80b1 net: hinic: fix the issue of CMDQ memory leaks
  (The involved file drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c is already deleted
    by the commit f1168d29 net/hinic: Update Hardware Abstract Layer))
0ce1ef335300 net: hinic: fix the issue of double release MBOX callback of VF
   (The involved function hinic_vf_func_init() is moved to other file.)

Total patches: 91 - 3 - 4 = 84 
 
Link:https://gitee.com/openeuler/kernel/pulls/807

 

Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 682685d0 d1fec5ec

arch/arc/include/asm/io.h

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ static inline void ioport_unmap(void __iomem *addr) 
{

}



extern void iounmap(const void __iomem *addr);

extern void iounmap(const volatile void __iomem *addr);



/*

 * io{read,write}{16,32}be() macros

arch/arc/mm/ioremap.c

+1 −1
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size, 
EXPORT_SYMBOL(ioremap_prot);





void iounmap(const void __iomem *addr)

void iounmap(const volatile void __iomem *addr)

{

	/* weird double cast to handle phys_addr_t > 32 bits */

	if (arc_uncached_addr_space((phys_addr_t)(u32)addr))

arch/arm64/include/asm/cpufeature.h

+6 −3
Original line number Diff line number Diff line
@@ -650,7 +650,8 @@ static inline bool system_supports_4kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN4_SHIFT);



	return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);

}



static inline bool system_supports_64kb_granule(void)
@@ -662,7 +663,8 @@ static inline bool system_supports_64kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN64_SHIFT);



	return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);

}



static inline bool system_supports_16kb_granule(void)
@@ -674,7 +676,8 @@ static inline bool system_supports_16kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN16_SHIFT);



	return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);

}



static inline bool system_supports_mixed_endian_el0(void)

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ 
#define ARM_CPU_IMP_HISI		0x48

#define ARM_CPU_IMP_PHYTIUM		0x70

#define ARM_CPU_IMP_APPLE		0x61

#define ARM_CPU_IMP_AMPERE		0xC0



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -120,6 +121,8 @@ 
#define APPLE_CPU_PART_M1_ICESTORM	0x022

#define APPLE_CPU_PART_M1_FIRESTORM	0x023



#define AMPERE_CPU_PART_AMPERE1		0xAC3



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -165,6 +168,7 @@ 
#define MIDR_FT_2500	 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2500)

#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)

#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

arch/arm64/include/asm/sysreg.h

+24 −12
Original line number Diff line number Diff line
@@ -857,14 +857,23 @@ 
#define ID_AA64MMFR0_PARANGE_SHIFT	0



#define ID_AA64MMFR0_TGRAN4_NI			0xf

#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN64_NI			0xf

#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN16_NI			0x0

#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf



#define ID_AA64MMFR0_PARANGE_48		0x5

#define ID_AA64MMFR0_PARANGE_52		0x6



#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2

#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7



#ifdef CONFIG_ARM64_PA_BITS_52

#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52

#else
@@ -1032,13 +1041,16 @@ 


#if defined(CONFIG_ARM64_4K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX

#elif defined(CONFIG_ARM64_64K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX

#endif



#define MVFR2_FPMISC_SHIFT		4