Commit ed202940 authored by Huang Shijie's avatar Huang Shijie Committed by David Woodhouse
Browse files

mtd: update the ABI document about the ecc step size 



We add a new sys node for ecc step size. So update the ABI document about it.

Signed-off-by: default avatarHuang Shijie <b32955@freescale.com>
Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
[Brian: edited description, modified 'ecc_strength']
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>

Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent f720e7ce

Documentation/ABI/testing/sysfs-class-mtd

+14 −3
Original line number Diff line number Diff line
@@ -128,9 +128,8 @@ KernelVersion: 3.4 
Contact:	linux-mtd@lists.infradead.org

Description:

		Maximum number of bit errors that the device is capable of

		correcting within each region covering an ecc step.  This will

		always be a non-negative integer.  Note that some devices will

		have multiple ecc steps within each writesize region.

		correcting within each region covering an ECC step (see

		ecc_step_size).  This will always be a non-negative integer.



		In the case of devices lacking any ECC capability, it is 0.
@@ -173,3 +172,15 @@ Description: 
		This is generally applicable only to NAND flash devices with ECC

		capability.  It is ignored on devices lacking ECC capability;

		i.e., devices for which ecc_strength is zero.



What:		/sys/class/mtd/mtdX/ecc_step_size

Date:		May 2013

KernelVersion:	3.10

Contact:	linux-mtd@lists.infradead.org

Description:

		The size of a single region covered by ECC, known as the ECC

		step.  Devices may have several equally sized ECC steps within

		each writesize region.



		It will always be a non-negative integer.  In the case of

		devices lacking any ECC capability, it is 0.