clk: remove sirf prima2/atlas drivers

* Clock and reset bindings for CSR atlas7

Required properties:

- compatible: Should be "sirf,atlas7-car"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- #reset-cells: Should be <1>

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.

The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c

The reset consumer should specify the desired reset by having the reset

ID in its "reset" phandle cell.

The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c

Examples: Clock and reset controller node:

car: clock-controller@18620000 {

	compatible = "sirf,atlas7-car";

	reg = <0x18620000 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Examples: Consumers using clock or reset:

timer@10dc0000 {

	compatible = "sirf,macro-tick";

	reg = <0x10dc0000 0x1000>;

	clocks = <&car 54>;

	interrupts = <0 0 0>,

		   <0 1 0>,

		   <0 2 0>,

		   <0 49 0>,

		   <0 50 0>,

		   <0 51 0>;

};

uart1: uart@18020000 {

	cell-index = <1>;

	compatible = "sirf,macro-uart";

	reg = <0x18020000 0x1000>;

	clocks = <&clks 95>;

	interrupts = <0 18 0>;

	fifosize = <32>;

};

vpp@13110000 {

	compatible = "sirf,prima2-vpp";

	reg = <0x13110000 0x10000>;

	interrupts = <0 31 0>;

	clocks = <&car 85>;

	resets = <&car 29>;

};

* Clock bindings for CSR SiRFprimaII

Required properties:

- compatible: Should be "sirf,prima2-clkc"

- reg: Address and length of the register set

- interrupts: Should contain clock controller interrupt

- #clock-cells: Should be <1>

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of prima2

clocks and IDs.

	Clock			ID

	---------------------------

	rtc			0

	osc             	1

	pll1            	2

	pll2            	3

	pll3            	4

	mem             	5

	sys             	6

	security        	7

	dsp             	8

	gps             	9

	mf              	10

	io              	11

	cpu             	12

	uart0           	13

	uart1           	14

	uart2           	15

	tsc             	16

	i2c0            	17

	i2c1            	18

	spi0            	19

	spi1            	20

	pwmc            	21

	efuse           	22

	pulse           	23

	dmac0           	24

	dmac1           	25

	nand            	26

	audio           	27

	usp0            	28

	usp1            	29

	usp2            	30

	vip             	31

	gfx             	32

	mm              	33

	lcd             	34

	vpp             	35

	mmc01           	36

	mmc23           	37

	mmc45           	38

	usbpll          	39

	usb0            	40

	usb1			41

Examples:

clks: clock-controller@88000000 {

	compatible = "sirf,prima2-clkc";

	reg = <0x88000000 0x1000>;

	interrupts = <3>;

	#clock-cells = <1>;

};

i2c0: i2c@b00e0000 {

	cell-index = <0>;

	compatible = "sirf,prima2-i2c";

	reg = <0xb00e0000 0x10000>;

	interrupts = <24>;

	clocks = <&clks 17>;

};

obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/

obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/

obj-$(CONFIG_CLK_SIFIVE)		+= sifive/

obj-$(CONFIG_ARCH_SIRF)			+= sirf/

obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/

obj-$(CONFIG_ARCH_AGILEX)		+= socfpga/

obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/

# SPDX-License-Identifier: GPL-2.0-only

#

# Makefile for sirf specific clk

#

obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o clk-atlas7.o

/* SPDX-License-Identifier: GPL-2.0 */

#define SIRFSOC_CLKC_CLK_EN0    0x0000

#define SIRFSOC_CLKC_CLK_EN1    0x0004

#define SIRFSOC_CLKC_REF_CFG    0x0020

#define SIRFSOC_CLKC_CPU_CFG    0x0024

#define SIRFSOC_CLKC_MEM_CFG    0x0028

#define SIRFSOC_CLKC_MEMDIV_CFG 0x002C

#define SIRFSOC_CLKC_SYS_CFG    0x0030

#define SIRFSOC_CLKC_IO_CFG     0x0034

#define SIRFSOC_CLKC_DSP_CFG    0x0038

#define SIRFSOC_CLKC_GFX_CFG    0x003c

#define SIRFSOC_CLKC_MM_CFG     0x0040

#define SIRFSOC_CLKC_GFX2D_CFG  0x0040

#define SIRFSOC_CLKC_LCD_CFG    0x0044

#define SIRFSOC_CLKC_MMC01_CFG  0x0048

#define SIRFSOC_CLKC_MMC23_CFG  0x004C

#define SIRFSOC_CLKC_MMC45_CFG  0x0050

#define SIRFSOC_CLKC_NAND_CFG	0x0054

#define SIRFSOC_CLKC_NANDDIV_CFG	0x0058

#define SIRFSOC_CLKC_PLL1_CFG0  0x0080

#define SIRFSOC_CLKC_PLL2_CFG0  0x0084

#define SIRFSOC_CLKC_PLL3_CFG0  0x0088

#define SIRFSOC_CLKC_PLL1_CFG1  0x008c

#define SIRFSOC_CLKC_PLL2_CFG1  0x0090

#define SIRFSOC_CLKC_PLL3_CFG1  0x0094

#define SIRFSOC_CLKC_PLL1_CFG2  0x0098

#define SIRFSOC_CLKC_PLL2_CFG2  0x009c

#define SIRFSOC_CLKC_PLL3_CFG2  0x00A0

#define SIRFSOC_USBPHY_PLL_CTRL 0x0008

#define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)

#define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)

#define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)