Unverified Commit ecca3ab8 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!11786 LTS patch backport 

Merge Pull Request from: @ci-robot 
 
PR sync from: Yuntao Liu <liuyuntao12@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/PR4NKFZ4OKINZIP4FWR5XFU6XFY7VGKK/ 
LTS patch backport

Amit Daniel Kachhap (1):
  arm64: cpufeature: Fix the visibility of compat hwcaps

Guanrui Huang (1):
  irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_alloc

James Morse (1):
  arm64: cpufeature: Force HWCAP to be based on the sysreg visible to
    user-space

Pali Rohár (1):
  irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1

Yipeng Zou (1):
  irqchip/mbigen: Fix mbigen node address layout


-- 
2.34.1
 
https://gitee.com/openeuler/kernel/issues/IATEDW 
 
Link:https://gitee.com/openeuler/kernel/pulls/11786

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarZhang Changzhong <zhangchangzhong@huawei.com>
parents e20d6993 b4a5b062

arch/arm64/kernel/cpufeature.c

+62 −17
Original line number Diff line number Diff line
@@ -279,6 +279,30 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_mvfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_mvfr1[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_mvfr2[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),		/* FPMisc */

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),		/* SIMDMisc */
@@ -294,10 +318,10 @@ static const struct arm64_ftr_bits ftr_dczid[] = { 


static const struct arm64_ftr_bits ftr_id_isar5[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),

	ARM64_FTR_END,

};
@@ -337,7 +361,7 @@ static const struct arm64_ftr_bits ftr_zcr[] = { 
 * Common ftr bits for a 32bit register with all hidden, strict

 * attributes, with 4bit feature fields and a default safe value of

 * 0. Covers the following 32bit registers:

 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]

 * id_isar[1-3], id_mmfr[1-3]

 */

static const struct arm64_ftr_bits ftr_generic_32bits[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
@@ -392,8 +416,8 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),



	/* Op1 = 0, CRn = 0, CRm = 3 */

	ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),

	ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),

	ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),



	/* Op1 = 0, CRn = 0, CRm = 4 */
@@ -862,20 +886,42 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 
	return val >= entry->min_field_value;

}



static bool

has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)

static u64

read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)

{

	u64 val;



	WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());

	if (scope == SCOPE_SYSTEM)

		val = read_sanitised_ftr_reg(entry->sys_reg);

		return read_sanitised_ftr_reg(entry->sys_reg);

	else

		val = __read_sysreg_by_encoding(entry->sys_reg);

		return __read_sysreg_by_encoding(entry->sys_reg);

}



static bool

has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)

{

	int mask;

	struct arm64_ftr_reg *regp;

	u64 val = read_scoped_sysreg(entry, scope);



	regp = get_arm64_ftr_reg(entry->sys_reg);

	if (!regp)

		return false;



	mask = cpuid_feature_extract_unsigned_field(regp->user_mask,

						    entry->field_pos);

	if (!mask)

		return false;



	return feature_matches(val, entry);

}



static bool

has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)

{

	u64 val = read_scoped_sysreg(entry, scope);

	return feature_matches(val, entry);

}



#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)

static bool has_cpuid_feature_lse(const struct arm64_cpu_capabilities *entry,

				  int scope)
@@ -1526,9 +1572,8 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
	{},

};





#define HWCAP_CPUID_MATCH(reg, field, s, min_value)		\

		.matches = has_cpuid_feature,			\

		.matches = has_user_cpuid_feature,		\

		.sys_reg = reg,					\

		.field_pos = field,				\

		.sign = s,					\
@@ -2012,7 +2057,7 @@ cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 


/*

 * We emulate only the following system register space.

 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]

 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]

 * See Table C5-6 System instruction encodings for System register accesses,

 * ARMv8 ARM(ARM DDI 0487A.f) for more details.

 */
@@ -2022,7 +2067,7 @@ static inline bool __attribute_const__ is_emulated(u32 id) 
		sys_reg_CRn(id) == 0x0 &&

		sys_reg_Op1(id) == 0x0 &&

		(sys_reg_CRm(id) == 0 ||

		 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));

		 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));

}



/*

drivers/irqchip/irq-armada-370-xp.c

+4 −0
Original line number Diff line number Diff line
@@ -350,6 +350,10 @@ static struct irq_chip armada_370_xp_irq_chip = { 
static int armada_370_xp_mpic_irq_map(struct irq_domain *h,

				      unsigned int virq, irq_hw_number_t hw)

{

	/* IRQs 0 and 1 cannot be mapped, they are handled internally */

	if (hw <= 1)

		return -EINVAL;



	armada_370_xp_irq_mask(irq_get_irq_data(virq));

	if (!is_percpu_irq(hw))

		writel(hw, per_cpu_int_base +

drivers/irqchip/irq-gic-v3-its.c

+0 −2
Original line number Diff line number Diff line
@@ -3477,8 +3477,6 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq 
	struct page *vprop_page;

	int base, nr_ids, i, err = 0;



	BUG_ON(!vm);



	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);

	if (!bitmap)

		return -ENOMEM;

drivers/irqchip/irq-mbigen.c

+16 −4
Original line number Diff line number Diff line
@@ -75,6 +75,20 @@ struct mbigen_device { 
	void __iomem		*base;

};



static inline unsigned int get_mbigen_node_offset(unsigned int nid)

{

	unsigned int offset = nid * MBIGEN_NODE_OFFSET;



	/*

	 * To avoid touched clear register in unexpected way, we need to directly

	 * skip clear register when access to more than 10 mbigen nodes.

	 */

	if (nid >= (REG_MBIGEN_CLEAR_OFFSET / MBIGEN_NODE_OFFSET))

		offset += MBIGEN_NODE_OFFSET;



	return offset;

}



static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)

{

	unsigned int nid, pin;
@@ -83,8 +97,7 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) 
	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;

	pin = hwirq % IRQS_PER_MBIGEN_NODE;



	return pin * 4 + nid * MBIGEN_NODE_OFFSET

			+ REG_MBIGEN_VEC_OFFSET;

	return pin * 4 + get_mbigen_node_offset(nid) + REG_MBIGEN_VEC_OFFSET;

}



static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
@@ -99,8 +112,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, 
	*mask = 1 << (irq_ofst % 32);

	ofst = irq_ofst / 32 * 4;



	*addr = ofst + nid * MBIGEN_NODE_OFFSET

		+ REG_MBIGEN_TYPE_OFFSET;

	*addr = ofst + get_mbigen_node_offset(nid) + REG_MBIGEN_TYPE_OFFSET;

}



static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,