Commit ec9e80ae authored by Wolfram Sang's avatar Wolfram Sang Committed by Ulf Hansson
Browse files

mmc: renesas_sdhi: add quirk for broken register layout 



Some early Gen3 SoCs have the DTRANEND1 bit at a different location than
all later SoCs. Because we need the bit soon, add a quirk so we know
which bit to use.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: default avatarDuy Nguyen <duy.nguyen.rh@renesas.com>
Tested-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221006190452.5316-5-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent af728d7a

drivers/mmc/host/renesas_sdhi.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct renesas_sdhi_quirks { 
	bool fixed_addr_mode;

	bool dma_one_rx_only;

	bool manual_tap_correction;

	bool old_info1_layout;

	u32 hs400_bad_taps;

	const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];

};

drivers/mmc/host/renesas_sdhi_internal_dmac.c

+3 −1
Original line number Diff line number Diff line
@@ -49,7 +49,8 @@ 
/* DM_CM_INFO1 and DM_CM_INFO1_MASK */

#define INFO1_CLEAR		0

#define INFO1_MASK_CLEAR	GENMASK_ULL(31, 0)

#define INFO1_DTRANEND1		BIT(17)

#define INFO1_DTRANEND1		BIT(20)

#define INFO1_DTRANEND1_OLD	BIT(17)

#define INFO1_DTRANEND0		BIT(16)



/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
@@ -165,6 +166,7 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { 
	.hs400_disabled = true,

	.hs400_4taps = true,

	.dma_one_rx_only = true,

	.old_info1_layout = true,

};



static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {