Commit ec9714bb authored by James Morse's avatar James Morse Committed by Jialin Zhang
Browse files

arm64: errata: Remove AES hwcap for COMPAT tasks 

stable inclusion
from stable-v5.10.152
commit 51b96ecaedc0a12f6827f189a94f59012dde8208
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I6O293

Reference:  https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=51b96ecaedc0a12f6827f189a94f59012dde8208



--------------------------------

commit 44b3834b upstream.

Cortex-A57 and Cortex-A72 have an erratum where an interrupt that
occurs between a pair of AES instructions in aarch32 mode may corrupt
the ELR. The task will subsequently produce the wrong AES result.

The AES instructions are part of the cryptographic extensions, which are
optional. User-space software will detect the support for these
instructions from the hwcaps. If the platform doesn't support these
instructions a software implementation should be used.

Remove the hwcap bits on affected parts to indicate user-space should
not use the AES instructions.

Acked-by: default avatarArd Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220714161523.279570-3-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
[florian: removed arch/arm64/tools/cpucaps and fixup cpufeature.c]
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>

conflicts:
    arch/arm64/Kconfig
    rch/arm64/include/asm/cpucaps.h
    rch/arm64/kernel/cpu_errata.c
    rch/arm64/kernel/cpufeature.c

Signed-off-by: default avatarLin Yujun <linyujun809@huawei.com>
Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parent 154050c2

Documentation/arm64/silicon-errata.rst

+4 −0
Original line number Diff line number Diff line
@@ -76,10 +76,14 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1319537        | ARM64_ERRATUM_1319367       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1742098        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #853709         | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1319367        | ARM64_ERRATUM_1319367       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1655431        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |

arch/arm64/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -497,6 +497,22 @@ config ARM64_ERRATUM_834220 


	  If unsure, say Y.



config ARM64_ERRATUM_1742098

    bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic     instructions in a sequence"

    depends on COMPAT

    default y

    help

      This option removes the AES hwcap for aarch32 user-space to

      workaround erratum 1742098 on Cortex-A57 and Cortex-A72.



      Affected parts may corrupt the AES state if an interrupt is

      taken between a pair of AES instructions. These instructions

      are only present if the cryptography extensions are present.

      All software should have a fallback implementation for CPUs

      that don't implement the cryptography extensions.

 

      If unsure, say Y.



config ARM64_ERRATUM_845719

	bool "Cortex-A53: 845719: a load might read incorrect data"

	depends on AARCH32_EL0

arch/arm64/include/asm/cpucaps.h

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ 
#define ARM64_HAS_ECV				64

#define ARM64_HAS_EPAN				65

#define ARM64_SPECTRE_BHB			66

#define ARM64_WORKAROUND_1742098	67



#define ARM64_NCAPS				80

arch/arm64/kernel/cpu_errata.c

+16 −0
Original line number Diff line number Diff line
@@ -428,6 +428,14 @@ static const struct midr_range erratum_1463225[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_1742098

static struct midr_range broken_aarch32_aes[] = {

	MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -627,6 +635,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
				  1, 0),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1742098

        {   

                .desc = "ARM erratum 1742098",

                .capability = ARM64_WORKAROUND_1742098,

                CAP_MIDR_RANGE_LIST(broken_aarch32_aes),

                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

        },  

#endif

#ifdef CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH

	{

		.desc = "HiSilicon HIP08 Cache Readunique Prefetch Disable",

arch/arm64/kernel/cpufeature.c

+12 −1
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ 
#include <asm/cpufeature.h>

#include <asm/cpu_ops.h>

#include <asm/fpsimd.h>

#include <asm/hwcap.h>

#include <asm/mmu_context.h>

#include <asm/mte.h>

#include <asm/processor.h>
@@ -1771,6 +1772,14 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 
}

#endif /* CONFIG_ARM64_MTE */



static void elf_hwcap_fixup(void)

{

#ifdef CONFIG_ARM64_ERRATUM_1742098

	if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))

		a32_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;

#endif /* ARM64_ERRATUM_1742098 */

}



/* Internal helper functions to match cpu capability type */

static bool

cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
@@ -2837,8 +2846,10 @@ void __init setup_cpu_features(void) 
	setup_system_capabilities();

	setup_elf_hwcaps(arm64_elf_hwcaps);



	if (system_supports_32bit_el0())

	if (system_supports_32bit_el0()) {

		setup_elf_hwcaps(a32_elf_hwcaps);

		elf_hwcap_fixup();

	}



	if (system_uses_ttbr0_pan())

		pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");