Commit ec94b9b2 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm: Add PG_dcache_clean to indicate dcache clean state 



This just add a better name for PG_arch_1. No functional change in this patch.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210203045812.234439-2-aneesh.kumar@linux.ibm.com
parent c7ba2d63

arch/powerpc/include/asm/cacheflush.h

+6 −0
Original line number Diff line number Diff line
@@ -8,6 +8,12 @@ 
#include <asm/cputable.h>

#include <asm/cpu_has_feature.h>



/*

 * This flag is used to indicate that the page pointed to by a pte is clean

 * and does not require cleaning before returning it to the user.

 */

#define PG_dcache_clean PG_arch_1



#ifdef CONFIG_PPC_BOOK3S_64

/*

 * Book3s has no ptesync after setting a pte, so without this ptesync it's

arch/powerpc/include/asm/kvm_ppc.h

+2 −2
Original line number Diff line number Diff line
@@ -881,9 +881,9 @@ static inline void kvmppc_mmu_flush_icache(kvm_pfn_t pfn) 


	/* Clear i-cache for new pages */

	page = pfn_to_page(pfn);

	if (!test_bit(PG_arch_1, &page->flags)) {

	if (!test_bit(PG_dcache_clean, &page->flags)) {

		flush_dcache_icache_page(page);

		set_bit(PG_arch_1, &page->flags);

		set_bit(PG_dcache_clean, &page->flags);

	}

}

arch/powerpc/mm/book3s64/hash_utils.c

+2 −2
Original line number Diff line number Diff line
@@ -1144,10 +1144,10 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) 
	page = pte_page(pte);



	/* page is dirty */

	if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {

	if (!test_bit(PG_dcache_clean, &page->flags) && !PageReserved(page)) {

		if (trap == 0x400) {

			flush_dcache_icache_page(page);

			set_bit(PG_arch_1, &page->flags);

			set_bit(PG_dcache_clean, &page->flags);

		} else

			pp |= HPTE_R_N;

	}

arch/powerpc/mm/mem.c

+2 −2
Original line number Diff line number Diff line
@@ -489,8 +489,8 @@ void flush_dcache_page(struct page *page) 
	if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))

		return;

	/* avoid an atomic op if possible */

	if (test_bit(PG_arch_1, &page->flags))

		clear_bit(PG_arch_1, &page->flags);

	if (test_bit(PG_dcache_clean, &page->flags))

		clear_bit(PG_dcache_clean, &page->flags);

}

EXPORT_SYMBOL(flush_dcache_page);

arch/powerpc/mm/pgtable.c

+7 −7
Original line number Diff line number Diff line
@@ -82,9 +82,9 @@ static pte_t set_pte_filter_hash(pte_t pte) 
		struct page *pg = maybe_pte_to_page(pte);

		if (!pg)

			return pte;

		if (!test_bit(PG_arch_1, &pg->flags)) {

		if (!test_bit(PG_dcache_clean, &pg->flags)) {

			flush_dcache_icache_page(pg);

			set_bit(PG_arch_1, &pg->flags);

			set_bit(PG_dcache_clean, &pg->flags);

		}

	}

	return pte;
@@ -117,13 +117,13 @@ static inline pte_t set_pte_filter(pte_t pte) 
		return pte;



	/* If the page clean, we move on */

	if (test_bit(PG_arch_1, &pg->flags))

	if (test_bit(PG_dcache_clean, &pg->flags))

		return pte;



	/* If it's an exec fault, we flush the cache and make it clean */

	if (is_exec_fault()) {

		flush_dcache_icache_page(pg);

		set_bit(PG_arch_1, &pg->flags);

		set_bit(PG_dcache_clean, &pg->flags);

		return pte;

	}
@@ -162,12 +162,12 @@ static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma, 
		goto bail;



	/* If the page is already clean, we move on */

	if (test_bit(PG_arch_1, &pg->flags))

	if (test_bit(PG_dcache_clean, &pg->flags))

		goto bail;



	/* Clean the page and set PG_arch_1 */

	/* Clean the page and set PG_dcache_clean */

	flush_dcache_icache_page(pg);

	set_bit(PG_arch_1, &pg->flags);

	set_bit(PG_dcache_clean, &pg->flags);



 bail:

	return pte_mkexec(pte);