Commit ec8b5b50 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add i.MX93 dtsi support 



The i.MX 93 applications processors are the first in the i.MX portfolio
to integrate the scalable Arm Cortex-A55 core, bringing performance
and energy efficiency to Linux-based edge applications and the
Arm Ethos-U65 microNPU, enabling developers to create more capable,
cost-effective and energy-efficient ML applications.

Add the basic dtsi support for i.MX93.

Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent f2906aa8

arch/arm64/boot/dts/freescale/imx93-pinfunc.h

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+623 −0

File added.

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arch/arm64/boot/dts/freescale/imx93.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2022 NXP

 */



#include <dt-bindings/clock/imx93-clock.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



#include "imx93-pinfunc.h"



/ {

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		mmc0 = &usdhc1;

		mmc1 = &usdhc2;

		mmc2 = &usdhc3;

		serial0 = &lpuart1;

		serial1 = &lpuart2;

		serial2 = &lpuart3;

		serial3 = &lpuart4;

		serial4 = &lpuart5;

		serial5 = &lpuart6;

		serial6 = &lpuart7;

		serial7 = &lpuart8;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		A55_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0>;

			enable-method = "psci";

			#cooling-cells = <2>;

		};



		A55_1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x100>;

			enable-method = "psci";

			#cooling-cells = <2>;

		};



	};



	osc_32k: clock-osc-32k {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <32768>;

		clock-output-names = "osc_32k";

	};



	osc_24m: clock-osc-24m {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <24000000>;

		clock-output-names = "osc_24m";

	};



	clk_ext1: clock-ext1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <133000000>;

		clock-output-names = "clk_ext1";

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;

		clock-frequency = <24000000>;

		arm,no-tick-in-suspend;

		interrupt-parent = <&gic>;

	};



	gic: interrupt-controller@48000000 {

		compatible = "arm,gic-v3";

		reg = <0 0x48000000 0 0x10000>,

		      <0 0x48040000 0 0xc0000>;

		#interrupt-cells = <3>;

		interrupt-controller;

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

	};



	soc@0 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x0 0x80000000>,

			 <0x28000000 0x0 0x28000000 0x10000000>;



		aips1: bus@44000000 {

			compatible = "fsl,aips-bus", "simple-bus";

			reg = <0x44000000 0x800000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			mu1: mailbox@44230000 {

				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";

				reg = <0x44230000 0x10000>;

				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

				#mbox-cells = <2>;

				status = "disabled";

			};



			system_counter: timer@44290000 {

				compatible = "nxp,sysctr-timer";

				reg = <0x44290000 0x30000>;

				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&osc_24m>;

				clock-names = "per";

			};



			lpuart1: serial@44380000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x44380000 0x1000>;

				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART1_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			lpuart2: serial@44390000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x44390000 0x1000>;

				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART2_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			iomuxc: pinctrl@443c0000 {

				compatible = "fsl,imx93-iomuxc";

				reg = <0x443c0000 0x10000>;

				status = "okay";

			};



			clk: clock-controller@44450000 {

				compatible = "fsl,imx93-ccm";

				reg = <0x44450000 0x10000>;

				#clock-cells = <1>;

				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;

				clock-names = "osc_32k", "osc_24m", "clk_ext1";

				status = "okay";

			};



			anatop: anatop@44480000 {

				compatible = "fsl,imx93-anatop", "syscon";

				reg = <0x44480000 0x10000>;

			};

		};



		aips2: bus@42000000 {

			compatible = "fsl,aips-bus", "simple-bus";

			reg = <0x42000000 0x800000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			mu2: mailbox@42440000 {

				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";

				reg = <0x42440000 0x10000>;

				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

				#mbox-cells = <2>;

				status = "disabled";

			};



			lpuart3: serial@42570000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x42570000 0x1000>;

				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART3_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			lpuart4: serial@42580000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x42580000 0x1000>;

				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART4_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			lpuart5: serial@42590000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x42590000 0x1000>;

				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART5_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			lpuart6: serial@425a0000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x425a0000 0x1000>;

				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART6_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			lpuart7: serial@42690000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x42690000 0x1000>;

				interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART7_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};



			lpuart8: serial@426a0000 {

				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";

				reg = <0x426a0000 0x1000>;

				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_LPUART8_GATE>;

				clock-names = "ipg";

				status = "disabled";

			};

		};



		aips3: bus@42800000 {

			compatible = "fsl,aips-bus", "simple-bus";

			reg = <0x42800000 0x800000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			usdhc1: mmc@42850000 {

				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";

				reg = <0x42850000 0x10000>;

				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_USDHC1_GATE>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <8>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step= <2>;

				status = "disabled";

			};



			usdhc2: mmc@42860000 {

				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";

				reg = <0x42860000 0x10000>;

				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_USDHC2_GATE>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step= <2>;

				status = "disabled";

			};



			usdhc3: mmc@428b0000 {

				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";

				reg = <0x428b0000 0x10000>;

				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_USDHC3_GATE>;

				clock-names = "ipg", "ahb", "per";

				bus-width = <4>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step= <2>;

				status = "disabled";

			};

		};



		gpio2: gpio@43810080 {

			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";

			reg = <0x43810080 0x1000>, <0x43810040 0x40>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&iomuxc 0 32 32>;

		};



		gpio3: gpio@43820080 {

			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";

			reg = <0x43820080 0x1000>, <0x43820040 0x40>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&iomuxc 0 64 32>;

		};



		gpio4: gpio@43830080 {

			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";

			reg = <0x43830080 0x1000>, <0x43830040 0x40>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&iomuxc 0 96 32>;

		};



		gpio1: gpio@47400080 {

			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";

			reg = <0x47400080 0x1000>, <0x47400040 0x40>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&iomuxc 0 0 32>;

		};

	};

};