Commit ec85362f authored by Emil Renner Berthing's avatar Emil Renner Berthing
Browse files

RISC-V: Add initial StarFive JH7100 device tree 



Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.

The CPU and cache data is based on the device tree in the vendor u-boot
port.

Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
parent b0ad20a3

arch/riscv/boot/dts/starfive/jh7100.dtsi

0 → 100644
+230 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0 OR MIT

/*

 * Copyright (C) 2021 StarFive Technology Co., Ltd.

 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>

 */



/dts-v1/;

#include <dt-bindings/clock/starfive-jh7100.h>

#include <dt-bindings/reset/starfive-jh7100.h>



/ {

	compatible = "starfive,jh7100";

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "sifive,u74-mc", "riscv";

			reg = <0>;

			d-cache-block-size = <64>;

			d-cache-sets = <64>;

			d-cache-size = <32768>;

			d-tlb-sets = <1>;

			d-tlb-size = <32>;

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <64>;

			i-cache-size = <32768>;

			i-tlb-sets = <1>;

			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			riscv,isa = "rv64imafdc";

			tlb-split;



			cpu0_intc: interrupt-controller {

				compatible = "riscv,cpu-intc";

				interrupt-controller;

				#interrupt-cells = <1>;

			};

		};



		cpu@1 {

			compatible = "sifive,u74-mc", "riscv";

			reg = <1>;

			d-cache-block-size = <64>;

			d-cache-sets = <64>;

			d-cache-size = <32768>;

			d-tlb-sets = <1>;

			d-tlb-size = <32>;

			device_type = "cpu";

			i-cache-block-size = <64>;

			i-cache-sets = <64>;

			i-cache-size = <32768>;

			i-tlb-sets = <1>;

			i-tlb-size = <32>;

			mmu-type = "riscv,sv39";

			riscv,isa = "rv64imafdc";

			tlb-split;



			cpu1_intc: interrupt-controller {

				compatible = "riscv,cpu-intc";

				interrupt-controller;

				#interrupt-cells = <1>;

			};

		};

	};



	osc_sys: osc_sys {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	osc_aud: osc_aud {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	gmac_rmii_ref: gmac_rmii_ref {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* Should be overridden by the board when needed */

		clock-frequency = <0>;

	};



	gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* Should be overridden by the board when needed */

		clock-frequency = <0>;

	};



	soc {

		compatible = "simple-bus";

		interrupt-parent = <&plic>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		clint: clint@2000000 {

			compatible = "starfive,jh7100-clint", "sifive,clint0";

			reg = <0x0 0x2000000 0x0 0x10000>;

			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7

					       &cpu1_intc 3 &cpu1_intc 7>;

		};



		plic: interrupt-controller@c000000 {

			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";

			reg = <0x0 0xc000000 0x0 0x4000000>;

			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9

					       &cpu1_intc 11 &cpu1_intc 9>;

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

			riscv,ndev = <127>;

		};



		clkgen: clock-controller@11800000 {

			compatible = "starfive,jh7100-clkgen";

			reg = <0x0 0x11800000 0x0 0x10000>;

			clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;

			clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";

			#clock-cells = <1>;

		};



		rstgen: reset-controller@11840000 {

			compatible = "starfive,jh7100-reset";

			reg = <0x0 0x11840000 0x0 0x10000>;

			#reset-cells = <1>;

		};



		i2c0: i2c@118b0000 {

			compatible = "snps,designware-i2c";

			reg = <0x0 0x118b0000 0x0 0x10000>;

			clocks = <&clkgen JH7100_CLK_I2C0_CORE>,

				 <&clkgen JH7100_CLK_I2C0_APB>;

			clock-names = "ref", "pclk";

			resets = <&rstgen JH7100_RSTN_I2C0_APB>;

			interrupts = <96>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c1: i2c@118c0000 {

			compatible = "snps,designware-i2c";

			reg = <0x0 0x118c0000 0x0 0x10000>;

			clocks = <&clkgen JH7100_CLK_I2C1_CORE>,

				 <&clkgen JH7100_CLK_I2C1_APB>;

			clock-names = "ref", "pclk";

			resets = <&rstgen JH7100_RSTN_I2C1_APB>;

			interrupts = <97>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		gpio: pinctrl@11910000 {

			compatible = "starfive,jh7100-pinctrl";

			reg = <0x0 0x11910000 0x0 0x10000>,

			      <0x0 0x11858000 0x0 0x1000>;

			reg-names = "gpio", "padctl";

			clocks = <&clkgen JH7100_CLK_GPIO_APB>;

			resets = <&rstgen JH7100_RSTN_GPIO_APB>;

			interrupts = <32>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		uart2: serial@12430000 {

			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";

			reg = <0x0 0x12430000 0x0 0x10000>;

			clocks = <&clkgen JH7100_CLK_UART2_CORE>,

				 <&clkgen JH7100_CLK_UART2_APB>;

			clock-names = "baudclk", "apb_pclk";

			resets = <&rstgen JH7100_RSTN_UART2_APB>;

			interrupts = <72>;

			reg-io-width = <4>;

			reg-shift = <2>;

			status = "disabled";

		};



		uart3: serial@12440000 {

			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";

			reg = <0x0 0x12440000 0x0 0x10000>;

			clocks = <&clkgen JH7100_CLK_UART3_CORE>,

				 <&clkgen JH7100_CLK_UART3_APB>;

			clock-names = "baudclk", "apb_pclk";

			resets = <&rstgen JH7100_RSTN_UART3_APB>;

			interrupts = <73>;

			reg-io-width = <4>;

			reg-shift = <2>;

			status = "disabled";

		};



		i2c2: i2c@12450000 {

			compatible = "snps,designware-i2c";

			reg = <0x0 0x12450000 0x0 0x10000>;

			clocks = <&clkgen JH7100_CLK_I2C2_CORE>,

				 <&clkgen JH7100_CLK_I2C2_APB>;

			clock-names = "ref", "pclk";

			resets = <&rstgen JH7100_RSTN_I2C2_APB>;

			interrupts = <74>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c3: i2c@12460000 {

			compatible = "snps,designware-i2c";

			reg = <0x0 0x12460000 0x0 0x10000>;

			clocks = <&clkgen JH7100_CLK_I2C3_CORE>,

				 <&clkgen JH7100_CLK_I2C3_APB>;

			clock-names = "ref", "pclk";

			resets = <&rstgen JH7100_RSTN_I2C3_APB>;

			interrupts = <75>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};

	};

};