Commit ec7b952f authored by Serge Semin's avatar Serge Semin Committed by Bjorn Helgaas
Browse files

PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists 

If the "snps,enable-cdm-check" property exists, we should enable the CDM
check.  But previously dw_pcie_setup() could exit before doing so if the
"num-lanes" property was absent or invalid.

Move the CDM enable earlier so we do it regardless of whether "num-lanes"
is present.

[bhelgaas: commit log]
Fixes: 07f123de ("PCI: dwc: Add support to enable CDM register check")
Link: https://lore.kernel.org/r/20220624143428.8334-7-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarVidya Sagar <vidyas@nvidia.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent 8161e962

drivers/pci/controller/dwc/pcie-designware.c

+7 −7
Original line number Diff line number Diff line
@@ -740,6 +740,13 @@ void dw_pcie_setup(struct dw_pcie *pci) 
	val |= PORT_LINK_DLL_LINK_EN;

	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);



	if (of_property_read_bool(np, "snps,enable-cdm-check")) {

		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);

		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |

		       PCIE_PL_CHK_REG_CHK_REG_START;

		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);

	}



	of_property_read_u32(np, "num-lanes", &pci->num_lanes);

	if (!pci->num_lanes) {

		dev_dbg(pci->dev, "Using h/w default number of lanes\n");
@@ -786,11 +793,4 @@ void dw_pcie_setup(struct dw_pcie *pci) 
		break;

	}

	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);



	if (of_property_read_bool(np, "snps,enable-cdm-check")) {

		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);

		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |

		       PCIE_PL_CHK_REG_CHK_REG_START;

		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);

	}

}