Commit ec648f6b authored by Emil Renner Berthing's avatar Emil Renner Berthing
Browse files

pinctrl: starfive: Add pinctrl driver for StarFive SoCs

Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.

For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.

I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.

Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf


Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Co-developed-by: default avatarHuan Feng <huan.feng@starfivetech.com>
Signed-off-by: default avatarHuan Feng <huan.feng@starfivetech.com>
Co-developed-by: default avatarDrew Fustini <drew@beagleboard.org>
Signed-off-by: default avatarDrew Fustini <drew@beagleboard.org>
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
parent 7431b391
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+8 −0
Original line number Diff line number Diff line
@@ -18137,6 +18137,14 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
F:	drivers/clk/starfive/clk-starfive-jh7100.c
F:	include/dt-bindings/clock/starfive-jh7100.h
STARFIVE JH7100 PINCTRL DRIVER
M:	Emil Renner Berthing <kernel@esmil.dk>
L:	linux-gpio@vger.kernel.org
S:	Maintained
F:	Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
F:	drivers/pinctrl/pinctrl-starfive.c
F:	include/dt-bindings/pinctrl/pinctrl-starfive.h
STARFIVE JH7100 RESET CONTROLLER DRIVER
M:	Emil Renner Berthing <kernel@esmil.dk>
S:	Maintained
+17 −0
Original line number Diff line number Diff line
@@ -281,6 +281,23 @@ config PINCTRL_ST
	select PINCONF
	select GPIOLIB_IRQCHIP

config PINCTRL_STARFIVE
	tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
	depends on SOC_STARFIVE || COMPILE_TEST
	depends on OF
	default SOC_STARFIVE
	select GENERIC_PINCTRL_GROUPS
	select GENERIC_PINMUX_FUNCTIONS
	select GENERIC_PINCONF
	select GPIOLIB
	select GPIOLIB_IRQCHIP
	select OF_GPIO
	help
	  Say yes here to support pin control on the StarFive JH7100 SoC.
	  This also provides an interface to the GPIO pins not used by other
	  peripherals supporting inputs, outputs, configuring pull-up/pull-down
	  and interrupts on input changes.

config PINCTRL_STMFX
	tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
	depends on I2C
+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_LPC18XX)	+= pinctrl-lpc18xx.o
obj-$(CONFIG_PINCTRL_TB10X)	+= pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) 	+= pinctrl-st.o
obj-$(CONFIG_PINCTRL_STARFIVE)	+= pinctrl-starfive.o
obj-$(CONFIG_PINCTRL_STMFX) 	+= pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_ZYNQ)	+= pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_ZYNQMP)	+= pinctrl-zynqmp.o
+1354 −0

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