Unverified Commit ec607b43 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!3129 [OLK-6.6] Driver for Zhaoxin AES and SHA algorithm 

Merge Pull Request from: @leoliu-oc 
 
Some Zhaoxin processors come with an integrated crypto engine (so called Zhaoxin ACE, Advanced Cryptography Engine) that provides instructions for very fast cryptographic operations with supported AES algorithms.

(The reason for modifying padlock-sha/aes: padlock-sha/aes are also what we are maintaining. The current patch is to refine it, and the old Ceantaur IDs Family6 CPUs and the newer Centaur IDs Family7 CPUs & Zhaoxin IDs CPUs will use different drivers.)

Include:
1. Add support for Zhaoxin AES algorithm
2. Add support for Zhaoxin SHA algorithm

### Issue
https://gitee.com/openeuler/kernel/issues/I8WXMN

### Default config Change
CONFIG_CRYPTO_DEV_ZHAOXIN=m
CONFIG_CRYPTO_DEV_ZHAOXIN_AES=m
CONFIG_CRYPTO_DEV_ZHAOXIN_SHA=m

### Test

1. Pass: The module is successfully installed and the AES algorithm function is correct
2. Pass: The module is successfully installed and the SHA algorithm function is correct 
 
Link:https://gitee.com/openeuler/kernel/pulls/3129

 

Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 7f86a51c 925ce56c

arch/x86/configs/openeuler_defconfig

+3 −0
Original line number Diff line number Diff line
@@ -8690,6 +8690,9 @@ CONFIG_CRYPTO_HW=y 
CONFIG_CRYPTO_DEV_PADLOCK=m

CONFIG_CRYPTO_DEV_PADLOCK_AES=m

CONFIG_CRYPTO_DEV_PADLOCK_SHA=m

CONFIG_CRYPTO_DEV_ZHAOXIN=m

CONFIG_CRYPTO_DEV_ZHAOXIN_AES=m

CONFIG_CRYPTO_DEV_ZHAOXIN_SHA=m

# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set

# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set

CONFIG_CRYPTO_DEV_CCP=y

drivers/crypto/Kconfig

+39 −0
Original line number Diff line number Diff line
@@ -52,6 +52,45 @@ config CRYPTO_DEV_PADLOCK_SHA 
	  If unsure say M. The compiled module will be

	  called padlock-sha.



config CRYPTO_DEV_ZHAOXIN

	tristate "Support for Zhaoxin ACE"

	depends on X86 && !UML

	help

	  Some Zhaoxin processors come with an integrated crypto engine

	  (so called Zhaoxin ACE, Advanced Cryptography Engine)

	  that provides instructions for very fast cryptographic

	  operations with supported algorithms.



	  The instructions are used only when the CPU supports them.

	  Otherwise software encryption is used.



config CRYPTO_DEV_ZHAOXIN_AES

	tristate "Zhaoxin ACE driver for AES algorithm"

	depends on CRYPTO_DEV_ZHAOXIN

	select CRYPTO_BLKCIPHER

	select CRYPTO_AES

	help

	  Use Zhaoxin ACE for AES algorithm.



	  Available in Zhaoxin CPUs.



	  If unsure say M. The compiled module will be

	  called zhaoxin-aes.



config CRYPTO_DEV_ZHAOXIN_SHA

	tristate "Zhaoxin ACE driver for SHA1 and SHA256 algorithms"

	depends on CRYPTO_DEV_ZHAOXIN

	select CRYPTO_HASH

	select CRYPTO_SHA1

	select CRYPTO_SHA256

	help

	  Use Zhaoxin ACE for SHA1/SHA256 algorithms.



	  Available in Zhaoxin processors.



	  If unsure say M. The compiled module will be

	  called zhaoxin-sha.



config CRYPTO_DEV_GEODE

	tristate "Support for the Geode LX AES engine"

	depends on X86_32 && PCI

drivers/crypto/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o 
obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o

obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o

obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o

obj-$(CONFIG_CRYPTO_DEV_ZHAOXIN_AES) += zhaoxin-aes.o

obj-$(CONFIG_CRYPTO_DEV_ZHAOXIN_SHA) += zhaoxin-sha.o

obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/

obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/

obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o

drivers/crypto/padlock-aes.c

+1 −1
Original line number Diff line number Diff line
@@ -475,7 +475,7 @@ static struct skcipher_alg cbc_aes_alg = { 
};



static const struct x86_cpu_id padlock_cpu_id[] = {

	X86_MATCH_FEATURE(X86_FEATURE_XCRYPT, NULL),

	X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 6, X86_FEATURE_XCRYPT, NULL),

	{}

};

MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);

drivers/crypto/padlock-sha.c

+1 −1
Original line number Diff line number Diff line
@@ -491,7 +491,7 @@ static struct shash_alg sha256_alg_nano = { 
};



static const struct x86_cpu_id padlock_sha_ids[] = {

	X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL),

	{ X86_VENDOR_CENTAUR, 6, X86_MODEL_ANY, X86_FEATURE_PHE },

	{}

};

MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);