Unverified Commit ec482c50 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!848 Support T6 ETM and Workaround CPU hung bug on hip09 

Merge Pull Request from: @hejunhao3 
 
1. Added support for HiSilicon T6 ETM
2. Fix CPU hold issue caused by hip09 ETM overflow 
 
Link:https://gitee.com/openeuler/kernel/pulls/848

 

Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 1f7abdfd eef6c034

drivers/hwtracing/coresight/coresight-etm4x-core.c

+14 −1
Original line number Diff line number Diff line
@@ -262,6 +262,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) 
#ifdef CONFIG_ETM4X_IMPDEF_FEATURE



#define HISI_HIP08_AMBA_ID		0x000b6d01

#define HISI_HIP09_AMBA_ID		0x000b6d02

#define ETM4_AMBA_MASK			0xfffff

#define HISI_HIP08_CORE_COMMIT_MASK	0x3000

#define HISI_HIP08_CORE_COMMIT_SHIFT	12
@@ -280,6 +281,11 @@ static bool etm4_hisi_match_pid(unsigned int id) 
	return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;

}



static bool etm4_hisi_hip09_match_pid(unsigned int id)

{

	return (id & ETM4_AMBA_MASK) == HISI_HIP09_AMBA_ID;

}



static void etm4_hisi_config_core_commit(void *info)

{

	bool enable = *(bool *)info;
@@ -302,9 +308,12 @@ static void etm4_hisi_config_core_commit(void *info) 
static void etm4_hisi_config_set_auxctrlr(void *info)

{

	struct csdev_access *csa = info;

	u32 trcauxctlr;



	/* Switch the ETM to idle state */

	etm4x_relaxed_write32(csa, HISI_HIP08_AUXCTRL_CHICKEN_BIT, TRCAUXCTLR);

	trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);

	trcauxctlr |= HISI_HIP08_AUXCTRL_CHICKEN_BIT;

	etm4x_relaxed_write32(csa, trcauxctlr, TRCAUXCTLR);

}



static struct etm4_arch_features etm4_features[] = {
@@ -355,6 +364,9 @@ static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 
		set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);

		set_bit(ETM4_IMPDEF_HISI_SET_AUXCTRLR, drvdata->arch_features);

	}



	if (etm4_hisi_hip09_match_pid(id))

		set_bit(ETM4_IMPDEF_HISI_SET_AUXCTRLR, drvdata->arch_features);

}

#else

static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
@@ -2118,6 +2130,7 @@ static const struct amba_id etm4_ids[] = { 
	CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */

	CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */

	CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */

	CS_AMBA_UCI_ID(0x000b6d45, uci_id_etm4),/* HiSilicon-T6 */

	{},

};

tools/perf/arch/arm/util/cs-etm.c

+6 −5
Original line number Diff line number Diff line
@@ -558,7 +558,7 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused, 


static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu)

{

	bool ret = false;

	bool ret = true;

	char path[PATH_MAX];

	int scan;

	unsigned int val;
@@ -570,10 +570,11 @@ static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu) 
	snprintf(path, PATH_MAX, "cpu%d/%s",

		 cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);

	scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);



	/* The file was read successfully, we have a winner */

	if (scan == 1)

		ret = true;

	if (scan != 1) {

		pr_err("%s: can't read file %s\n",

		       CORESIGHT_ETM_PMU_NAME, path);

		ret = false;

	}



	return ret;

}