dt-bindings: opp: Convert qcom-nvmem-cpufreq to DT schema (ec24d1d5) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings

		maintainers:
		- Ilia Lin <ilia.lin@kernel.org>

		description: \|
		In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
		voltage is dynamically configured by Core Power Reduction (CPR) depending on
		current CPU frequency and efuse values.
		CPR provides a power domain with multiple levels that are selected depending
		on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
		according to the required OPPs defined in the CPU OPP tables.

		select:
		properties:
		compatible:
		contains:
		enum:
		- qcom,qcs404
		required:
		- compatible

		properties:
		cpus:
		type: object

		patternProperties:
		'cpu@[0-9a-f]+':
		type: object

		properties:
		power-domains:
		maxItems: 1

		power-domain-names:
		items:
		- const: cpr

		required:
		- power-domains
		- power-domain-names

		patternProperties:
		'^opp-table(-[a-z0-9]+)?$':
		if:
		properties:
		compatible:
		const: operating-points-v2-kryo-cpu
		then:
		patternProperties:
		'^opp-?[0-9]+$':
		required:
		- required-opps

		additionalProperties: true

		examples:
		- \|
		/ {
		model = "Qualcomm Technologies, Inc. QCS404";
		compatible = "qcom,qcs404";
		#address-cells = <2>;
		#size-cells = <2>;

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x100>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		next-level-cache = <&L2_0>;
		#cooling-cells = <2>;
		clocks = <&apcs_glb>;
		operating-points-v2 = <&cpu_opp_table>;
		power-domains = <&cpr>;
		power-domain-names = "cpr";
		};

		CPU1: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x101>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		next-level-cache = <&L2_0>;
		#cooling-cells = <2>;
		clocks = <&apcs_glb>;
		operating-points-v2 = <&cpu_opp_table>;
		power-domains = <&cpr>;
		power-domain-names = "cpr";
		};

		CPU2: cpu@102 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x102>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		next-level-cache = <&L2_0>;
		#cooling-cells = <2>;
		clocks = <&apcs_glb>;
		operating-points-v2 = <&cpu_opp_table>;
		power-domains = <&cpr>;
		power-domain-names = "cpr";
		};

		CPU3: cpu@103 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x103>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		next-level-cache = <&L2_0>;
		#cooling-cells = <2>;
		clocks = <&apcs_glb>;
		operating-points-v2 = <&cpu_opp_table>;
		power-domains = <&cpr>;
		power-domain-names = "cpr";
		};
		};

		cpu_opp_table: opp-table-cpu {
		compatible = "operating-points-v2-kryo-cpu";
		opp-shared;

		opp-1094400000 {
		opp-hz = /bits/ 64 <1094400000>;
		required-opps = <&cpr_opp1>;
		};
		opp-1248000000 {
		opp-hz = /bits/ 64 <1248000000>;
		required-opps = <&cpr_opp2>;
		};
		opp-1401600000 {
		opp-hz = /bits/ 64 <1401600000>;
		required-opps = <&cpr_opp3>;
		};
		};

		cpr_opp_table: opp-table-cpr {
		compatible = "operating-points-v2-qcom-level";

		cpr_opp1: opp1 {
		opp-level = <1>;
		qcom,opp-fuse-level = <1>;
		};
		cpr_opp2: opp2 {
		opp-level = <2>;
		qcom,opp-fuse-level = <2>;
		};
		cpr_opp3: opp3 {
		opp-level = <3>;
		qcom,opp-fuse-level = <3>;
		};
		};
		};

Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm Technologies, Inc. NVMEM OPP bindings

		maintainers:
		- Ilia Lin <ilia.lin@kernel.org>

		allOf:
		- $ref: opp-v2-base.yaml#

		description: \|
		In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
		the CPU frequencies subset and voltage value of each OPP varies based on
		the silicon variant in use.
		Qualcomm Technologies, Inc. Process Voltage Scaling Tables
		defines the voltage and frequency value based on the msm-id in SMEM
		and speedbin blown in the efuse combination.
		The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
		to provide the OPP framework with required information (existing HW bitmap).
		This is used to determine the voltage and frequency value for each OPP of
		operating-points-v2 table when it is parsed by the OPP framework.

		properties:
		compatible:
		const: operating-points-v2-kryo-cpu

		nvmem-cells:
		description: \|
		A phandle pointing to a nvmem-cells node representing the
		efuse registers that has information about the
		speedbin that is used to select the right frequency/voltage
		value pair.

		opp-shared: true

		patternProperties:
		'^opp-?[0-9]+$':
		type: object

		properties:
		opp-hz: true

		opp-microvolt: true

		opp-supported-hw:
		description: \|
		A single 32 bit bitmap value, representing compatible HW.
		Bitmap:
		0: MSM8996 V3, speedbin 0
		1: MSM8996 V3, speedbin 1
		2: MSM8996 V3, speedbin 2
		3: unused
		4: MSM8996 SG, speedbin 0
		5: MSM8996 SG, speedbin 1
		6: MSM8996 SG, speedbin 2
		7-31: unused
		maximum: 0x77

		clock-latency-ns: true

		required-opps: true

		required:
		- opp-hz

		required:
		- compatible

		if:
		required:
		- nvmem-cells
		then:
		patternProperties:
		'^opp-?[0-9]+$':
		required:
		- opp-supported-hw

		additionalProperties: false

		examples:
		- \|
		/ {
		model = "Qualcomm Technologies, Inc. DB820c";
		compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
		#address-cells = <2>;
		#size-cells = <2>;

		cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x0>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		clocks = <&kryocc 0>;
		operating-points-v2 = <&cluster0_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_0>;
		L2_0: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		};
		};

		CPU1: cpu@1 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x1>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		clocks = <&kryocc 0>;
		operating-points-v2 = <&cluster0_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x100>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		clocks = <&kryocc 1>;
		operating-points-v2 = <&cluster1_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_1>;
		L2_1: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		};
		};

		CPU3: cpu@101 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x101>;
		enable-method = "psci";
		cpu-idle-states = <&CPU_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
		clocks = <&kryocc 1>;
		operating-points-v2 = <&cluster1_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_1>;
		};

		cpu-map {
		cluster0 {
		core0 {
		cpu = <&CPU0>;
		};

		core1 {
		cpu = <&CPU1>;
		};
		};

		cluster1 {
		core0 {
		cpu = <&CPU2>;
		};

		core1 {
		cpu = <&CPU3>;
		};
		};
		};
		};

		cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2-kryo-cpu";
		nvmem-cells = <&speedbin_efuse>;
		opp-shared;

		opp-307200000 {
		opp-hz = /bits/ 64 <307200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x77>;
		clock-latency-ns = <200000>;
		};
		opp-1593600000 {
		opp-hz = /bits/ 64 <1593600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x71>;
		clock-latency-ns = <200000>;
		};
		opp-2188800000 {
		opp-hz = /bits/ 64 <2188800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x10>;
		clock-latency-ns = <200000>;
		};
		};

		cluster1_opp: opp-table-1 {
		compatible = "operating-points-v2-kryo-cpu";
		nvmem-cells = <&speedbin_efuse>;
		opp-shared;

		opp-307200000 {
		opp-hz = /bits/ 64 <307200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x77>;
		clock-latency-ns = <200000>;
		};
		opp-1593600000 {
		opp-hz = /bits/ 64 <1593600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-2150400000 {
		opp-hz = /bits/ 64 <2150400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x31>;
		clock-latency-ns = <200000>;
		};
		opp-2342400000 {
		opp-hz = /bits/ 64 <2342400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x10>;
		clock-latency-ns = <200000>;
		};
		};

		smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
		};

		soc {
		#address-cells = <1>;
		#size-cells = <1>;

		qfprom: qfprom@74000 {
		compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
		reg = <0x00074000 0x8ff>;
		#address-cells = <1>;
		#size-cells = <1>;

		speedbin_efuse: speedbin@133 {
		reg = <0x133 0x1>;
		bits = <5 3>;
		};
		};
		};
		};

Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt

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MAINTAINERS

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		@@ -15940,7 +15940,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
		M: Ilia Lin <ilia.lin@kernel.org>
		L: linux-pm@vger.kernel.org
		S: Maintained
		F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
		F: Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
		F: Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
		F: drivers/cpufreq/qcom-cpufreq-nvmem.c

		QUALCOMM CRYPTO DRIVERS