Merge airlied/drm-next into drm-intel-next-queued

Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>

Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>

Takashi YOSHII <takashi.yoshii.zj@renesas.com>

Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>

Yusuke Goda <goda.yusuke@renesas.com>

Gustavo Padovan <gustavo@las.ic.unicamp.br>

Gustavo Padovan <padovan@profusion.mobi>

/* Fixed header pattern */

header:		.byte	0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00

mfg_id:		.word	swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))

mfg_id:		.hword	swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))

prod_code:	.word	0

prod_code:	.hword	0

/* Serial number. 32 bits, little endian. */

serial_number:	.long	SERIAL

descriptor1:

/* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */

clock:		.word	CLOCK/10

clock:		.hword	CLOCK/10

/* Horizontal active pixels 8 lsbits (0-4095) */

x_act_lsb:	.byte	XPIX&0xff

			kernel and module base offset ASLR (Address Space

			Layout Randomization).

	kasan_multi_shot

			[KNL] Enforce KASAN (Kernel Address Sanitizer) to print

			report on every invalid memory access. Without this

			parameter KASAN will print report only for the first

			invalid access.

	keepinitrd	[HW,ARM]

	kernelcore=	[KNL,X86,IA-64,PPC]

Amlogic specific extensions to the Synopsys Designware HDMI Controller

======================================================================

The Amlogic Meson Synopsys Designware Integration is composed of :

- A Synopsys DesignWare HDMI Controller IP

- A TOP control block controlling the Clocks and PHY

- A custom HDMI PHY in order to convert video to TMDS signal

 ___________________________________

|            HDMI TOP               |<= HPD

|___________________________________|

|                  |                |

|  Synopsys HDMI   |   HDMI PHY     |=> TMDS

|    Controller    |________________|

|___________________________________|<=> DDC

The HDMI TOP block only supports HPD sensing.

The Synopsys HDMI Controller interrupt is routed through the

TOP Block interrupt.

Communication to the TOP Block and the Synopsys HDMI Controller is done

via a pair of dedicated addr+read/write registers.

The HDMI PHY is configured by registers in the HHI register block.

Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux

selects either the ENCI encoder for the 576i or 480i formats or the ENCP

encoder for all the other formats including interlaced HD formats.

The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate

DVI timings for the HDMI controller.

Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare

HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF

audio source interfaces.

Required properties:

- compatible: value should be different for each SoC family as :

	- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"

	- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"

	- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"

	followed by the common "amlogic,meson-gx-dw-hdmi"

- reg: Physical base address and length of the controller's registers.

- interrupts: The HDMI interrupt number

- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,

  and the Amlogic Meson venci clocks as described in

  Documentation/devicetree/bindings/clock/clock-bindings.txt,

  the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"

- resets, resets-names: must have the phandles to the HDMI apb, glue and phy

  resets as described in :

  Documentation/devicetree/bindings/reset/reset.txt,

  the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"

Required nodes:

The connections to the HDMI ports are modeled using the OF graph

bindings specified in Documentation/devicetree/bindings/graph.txt.

The following table lists for each supported model the port number

corresponding to each HDMI output and input.

		Port 0		Port 1

-----------------------------------------

 S905 (GXBB)	VENC Input	TMDS Output

 S905X (GXL)	VENC Input	TMDS Output

 S905D (GXL)	VENC Input	TMDS Output

 S912 (GXM)	VENC Input	TMDS Output

Example:

hdmi-connector {

	compatible = "hdmi-connector";

	type = "a";

	port {

		hdmi_connector_in: endpoint {

			remote-endpoint = <&hdmi_tx_tmds_out>;

		};

	};

};

hdmi_tx: hdmi-tx@c883a000 {

	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";

	reg = <0x0 0xc883a000 0x0 0x1c>;

	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;

	resets = <&reset RESET_HDMITX_CAPB3>,

		 <&reset RESET_HDMI_SYSTEM_RESET>,

		 <&reset RESET_HDMI_TX>;

	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";

	clocks = <&clkc CLKID_HDMI_PCLK>,

		 <&clkc CLKID_CLK81>,

		 <&clkc CLKID_GCLK_VENCI_INT0>;

	clock-names = "isfr", "iahb", "venci";

	#address-cells = <1>;

	#size-cells = <0>;

	/* VPU VENC Input */

	hdmi_tx_venc_port: port@0 {

		reg = <0>;

		hdmi_tx_in: endpoint {

			remote-endpoint = <&hdmi_tx_out>;

		};

	};

	/* TMDS Output */

	hdmi_tx_tmds_port: port@1 {

		reg = <1>;

		hdmi_tx_tmds_out: endpoint {

			remote-endpoint = <&hdmi_connector_in>;

		};

	};

};

Renesas Gen3 DWC HDMI TX Encoder

================================

The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP

with a companion PHY IP.

These DT bindings follow the Synopsys DWC HDMI TX bindings defined in

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the

following device-specific properties.

Required properties:

- compatible : Shall contain one or more of

  - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX

  - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX

    When compatible with generic versions, nodes must list the SoC-specific

    version corresponding to the platform first, followed by the

    family-specific version.

- reg: See dw_hdmi.txt.

- interrupts: HDMI interrupt number

- clocks: See dw_hdmi.txt.

- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.

- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0

  corresponding to the video input of the controller and one port numbered 1

  corresponding to its HDMI output. Each port shall have a single endpoint.

Optional properties:

- power-domains: Shall reference the power domain that contains the DWC HDMI,

  if any.

Example:

	hdmi0: hdmi0@fead0000 {

		compatible = "renesas,r8a7795-dw-hdmi";

		reg = <0 0xfead0000 0 0x10000>;

		interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;

		clock-names = "iahb", "isfr";

		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

		status = "disabled";

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				dw_hdmi0_in: endpoint {

					remote-endpoint = <&du_out_hdmi0>;

				};

			};

			port@1 {

				reg = <1>;

				rcar_dw_hdmi0_out: endpoint {

					remote-endpoint = <&hdmi0_con>;

				};

			};

		};

	};

	hdmi0-out {

		compatible = "hdmi-connector";

		label = "HDMI0 OUT";

		type = "a";

		port {

			hdmi0_con: endpoint {

				remote-endpoint = <&rcar_dw_hdmi0_out>;

			};

		};

	};