Commit ebe82cf9 authored by Joakim Tjernlund's avatar Joakim Tjernlund Committed by Wolfram Sang
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i2c: mpc: Correct I2C reset procedure 



Current I2C reset procedure is broken in two ways:
1) It only generate 1 START instead of 9 STARTs and STOP.
2) It leaves the bus Busy so every I2C xfer after the first
   fixup calls the reset routine again, for every xfer there after.

This fixes both errors.

Signed-off-by: default avatarJoakim Tjernlund <joakim.tjernlund@infinera.com>
Acked-by: default avatarScott Wood <oss@buserror.net>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent 1ead7e99

drivers/i2c/busses/i2c-mpc.c

+15 −8
Original line number Diff line number Diff line
@@ -119,23 +119,30 @@ static inline void writeccr(struct mpc_i2c *i2c, u32 x) 
/* Sometimes 9th clock pulse isn't generated, and slave doesn't release

 * the bus, because it wants to send ACK.

 * Following sequence of enabling/disabling and sending start/stop generates

 * the 9 pulses, so it's all OK.

 * the 9 pulses, each with a START then ending with STOP, so it's all OK.

 */

static void mpc_i2c_fixup(struct mpc_i2c *i2c)

{

	int k;

	u32 delay_val = 1000000 / i2c->real_clk + 1;



	if (delay_val < 2)

		delay_val = 2;

	unsigned long flags;



	for (k = 9; k; k--) {

		writeccr(i2c, 0);

		writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);

		writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */

		writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */

		readb(i2c->base + MPC_I2C_DR); /* init xfer */

		udelay(15); /* let it hit the bus */

		local_irq_save(flags); /* should not be delayed further */

		writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */

		readb(i2c->base + MPC_I2C_DR);

		writeccr(i2c, CCR_MEN);

		udelay(delay_val << 1);

		if (k != 1)

			udelay(5);

		local_irq_restore(flags);

	}

	writeccr(i2c, CCR_MEN); /* Initiate STOP */

	readb(i2c->base + MPC_I2C_DR);

	udelay(15); /* Let STOP propagate */

	writeccr(i2c, 0);

}



static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)