Commit ebe5ffd8 authored Nov 12, 2021 by Stylon Wang Committed by Alex Deucher Dec 01, 2021

drm/amd/display: Enable P010 for DCN3x ASICs



[Why + How]
Enable P010 for SDR video applications.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent c022375a

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -816,7 +816,7 @@ static const struct dc_plane_cap plane_cap = {
		.argb8888 = true,
		.nv12 = true,
		.fp16 = true,
		.p010 = false,
		.p010 = true,
		.ayuv = false,
		},

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -656,7 +656,7 @@ static const struct dc_plane_cap plane_cap = {
		.argb8888 = true,
		.nv12 = true,
		.fp16 = true,
		.p010 = false,
		.p010 = true,
		.ayuv = false,
		},

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -276,7 +276,7 @@ static const struct dc_plane_cap plane_cap = {
		.argb8888 = true,
		.nv12 = true,
		.fp16 = true,
		.p010 = false,
		.p010 = true,
		.ayuv = false,
		},
		.max_upscale_factor = {

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -254,7 +254,7 @@ static const struct dc_plane_cap plane_cap = {
		.argb8888 = true,
		.nv12 = true,
		.fp16 = true,
		.p010 = false,
		.p010 = true,
		.ayuv = false,
		},
		.max_upscale_factor = {

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -968,7 +968,7 @@ static const struct dc_plane_cap plane_cap = {
		.argb8888 = true,
		.nv12 = true,
		.fp16 = true,
		.p010 = false,
		.p010 = true,
		.ayuv = false,
		},