Commit ebd9aea1 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Will Deacon
Browse files

arm64: head: drop idmap_ptrs_per_pgd 



The assignment of idmap_ptrs_per_pgd lacks any cache invalidation, even
though it is updated with the MMU and caches disabled. However, we never
bother to read the value again except in the very next instruction, and
so we can just drop the variable entirely.

Signed-off-by: default avatarArd Biesheuvel <ardb@kernel.org>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20220624150651.1358849-5-ardb@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent e8d13cce

arch/arm64/include/asm/mmu_context.h

+0 −1
Original line number Diff line number Diff line
@@ -61,7 +61,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) 
 * physical memory, in which case it will be smaller.

 */

extern int idmap_t0sz;

extern u64 idmap_ptrs_per_pgd;



/*

 * Ensure TCR.T0SZ is set to the provided value.

arch/arm64/kernel/head.S

+3 −4
Original line number Diff line number Diff line
@@ -300,6 +300,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables) 
	 * range in that case, and configure an additional translation level

	 * if needed.

	 */

	mov	x4, #PTRS_PER_PGD

	idmap_get_t0sz x5

	cmp	x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough?

	b.ge	1f			// .. then skip VA range extension
@@ -319,18 +320,16 @@ SYM_FUNC_START_LOCAL(__create_page_tables) 
#error "Mismatch between VA_BITS and page size/number of translation levels"

#endif



	mov	x4, EXTRA_PTRS

	create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6

	mov	x2, EXTRA_PTRS

	create_table_entry x0, x3, EXTRA_SHIFT, x2, x5, x6

#else

	/*

	 * If VA_BITS == 48, we don't have to configure an additional

	 * translation level, but the top-level table has more entries.

	 */

	mov	x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)

	str_l	x4, idmap_ptrs_per_pgd, x5

#endif

1:

	ldr_l	x4, idmap_ptrs_per_pgd

	adr_l	x6, __idmap_text_end		// __pa(__idmap_text_end)



	map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14

arch/arm64/mm/mmu.c

+0 −1
Original line number Diff line number Diff line
@@ -44,7 +44,6 @@ 
#define NO_EXEC_MAPPINGS	BIT(2)	/* assumes FEAT_HPDS is not used */



int idmap_t0sz __ro_after_init;

u64 idmap_ptrs_per_pgd = PTRS_PER_PGD;



#if VA_BITS > 48

u64 vabits_actual __ro_after_init = VA_BITS_MIN;