Commit ebb4e2b0 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Rename skl+ scaler binding bits 



Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.

v2: Don't break gvt

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230426135019.7603-4-ville.syrjala@linux.intel.com
parent 33d233f5

drivers/gpu/drm/i915/display/skl_scaler.c

+6 −6
Original line number Diff line number Diff line
@@ -396,7 +396,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat 
			mode = PS_SCALER_MODE_PLANAR;



			if (linked)

				mode |= PS_PLANE_Y_SEL(linked->id);

				mode |= PS_BINDING_Y_PLANE(linked->id);

		}

	} else if (DISPLAY_VER(dev_priv) >= 10) {

		mode = PS_SCALER_MODE_NORMAL;
@@ -741,8 +741,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) 


	id = scaler_state->scaler_id;



	ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);

	ps_ctrl |=  PS_SCALER_EN | scaler_state->scalers[id].mode;

	ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |

		skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);



	skl_scaler_setup_filter(dev_priv, pipe, id, 0,

				crtc_state->hw.scaling_filter);
@@ -804,8 +804,8 @@ skl_program_plane_scaler(struct intel_plane *plane, 
		uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);

	}



	ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);

	ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;

	ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |

		skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);



	skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,

				plane_state->hw.scaling_filter);
@@ -870,7 +870,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) 
		u32 ctl, pos, size;



		ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));

		if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)

		if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))

			continue;



		id = i;

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Diff line number Diff line
@@ -1562,7 +1562,7 @@ static int pf_write(struct intel_vgpu *vgpu, 


	if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||

	   offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||

	   offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {

	   offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {

		drm_WARN_ONCE(&i915->drm, true,

			      "VM(%d): guest is trying to scaling a plane\n",

			      vgpu->id);

drivers/gpu/drm/i915/i915_reg.h

+5 −4
Original line number Diff line number Diff line
@@ -4051,8 +4051,9 @@ 
#define SKL_PS_SCALER_MODE_NV12 (2 << 28)

#define PS_SCALER_MODE_PLANAR (1 << 29)

#define PS_SCALER_MODE_NORMAL (0 << 29)

#define PS_PLANE_SEL_MASK  (7 << 25)

#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)

#define PS_BINDING_MASK (7 << 25)

#define PS_BINDING_PIPE (0 << 25)

#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)

#define PS_FILTER_MASK         (3 << 23)

#define PS_FILTER_MEDIUM       (0 << 23)

#define PS_FILTER_PROGRAMMED   (1 << 23)
@@ -4068,8 +4069,8 @@ 
#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)

#define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)

#define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)

#define PS_PLANE_Y_SEL_MASK  (7 << 5)

#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)

#define PS_BINDING_Y_MASK  (7 << 5)

#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)

#define PS_Y_VERT_FILTER_SELECT(set)   ((set) << 4)

#define PS_Y_HORZ_FILTER_SELECT(set)   ((set) << 3)

#define PS_UV_VERT_FILTER_SELECT(set)  ((set) << 2)