Unverified Commit eb9dfdd1 authored by Dom Cobley's avatar Dom Cobley Committed by Maxime Ripard
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drm/vc4: crtc: Reduce PV fifo threshold on hvs4 



Experimentally have found PV on hvs4 reports fifo full
error with expected settings and does not with one less

This appears as:
[drm:drm_atomic_helper_wait_for_flip_done] *ERROR* [CRTC:82:crtc-3] flip_done timed out

with bit 10 of PV_STAT set "HVS driving pixels when the PV FIFO is full"

Fixes: c8b75bca ("drm/vc4: Add KMS support for Raspberry Pi.")
Signed-off-by: default avatarDom Cobley <popcornmix@gmail.com>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20210318161328.1471556-3-maxime@cerno.tech
parent 35d65ab3

drivers/gpu/drm/vc4/vc4_crtc.c

+17 −0
Original line number Diff line number Diff line
@@ -210,6 +210,7 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 
{

	const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);

	const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);

	struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);

	u32 fifo_len_bytes = pv_data->fifo_depth;



	/*
@@ -238,6 +239,22 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 
		if (crtc_data->hvs_output == 5)

			return 32;



		/*

		 * It looks like in some situations, we will overflow

		 * the PixelValve FIFO (with the bit 10 of PV stat being

		 * set) and stall the HVS / PV, eventually resulting in

		 * a page flip timeout.

		 *

		 * Displaying the video overlay during a playback with

		 * Kodi on an RPi3 seems to be a great solution with a

		 * failure rate around 50%.

		 *

		 * Removing 1 from the FIFO full level however

		 * seems to completely remove that issue.

		 */

		if (!vc4->hvs->hvs5)

			return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;



		return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;

	}

}