Commit eb962fae authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehpsdv: Add maximum sseu limits 



Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarCaz Yokoyama <caz.yokoyama@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-10-matthew.d.roper@intel.com
parent 05b78d29

drivers/gpu/drm/i915/gt/intel_sseu.c

+4 −1
Original line number Diff line number Diff line
@@ -145,6 +145,9 @@ static void gen12_sseu_info_init(struct intel_gt *gt) 
	 * across the entire device. Then calculate out the DSS for each

	 * workload type within that software slice.

	 */

	if (IS_XEHPSDV(gt->i915))

		intel_sseu_set_info(sseu, 1, 32, 16);

	else

		intel_sseu_set_info(sseu, 1, 6, 16);



	/*

drivers/gpu/drm/i915/gt/intel_sseu.h

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ struct intel_gt; 
struct drm_printer;



#define GEN_MAX_SLICES		(3) /* SKL upper bound */

#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */

#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */

#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)

#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)

#define GEN_MAX_EUS		(16) /* TGL upper bound */

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt, 
static void gen11_sseu_device_status(struct intel_gt *gt,

				     struct sseu_dev_info *sseu)

{

#define SS_MAX 6

#define SS_MAX 8

	struct intel_uncore *uncore = gt->uncore;

	const struct intel_gt_info *info = &gt->info;

	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];