Commit eb829e54 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add DMAC clocks/resets 



Add DMAC clock and reset entries in CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-10-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1962dd36

drivers/clk/renesas/r9a07g044-cpg.c

+8 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ enum clk_ids { 
	CLK_PLL5,

	CLK_PLL5_DIV2,

	CLK_PLL6,

	CLK_P1_DIV2,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -79,6 +80,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),

	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,

		DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),

	DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,

		DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

};
@@ -90,6 +92,10 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x518, 0),

	DEF_MOD("ia55_clk",	R9A07G044_IA55_CLK, R9A07G044_CLK_P1,

				0x518, 1),

	DEF_MOD("dmac_aclk",	R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,

				0x52c, 0),

	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,

				0x52c, 1),

	DEF_MOD("i2c0",		R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,

				0x580, 0),

	DEF_MOD("i2c1",		R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
@@ -116,6 +122,8 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),

	DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),

	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),

	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),

	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),

	DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),

	DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),

	DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),