Unverified Commit eb746180 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Palmer Dabbelt
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riscv: dma-mapping: only invalidate after DMA, not flush 



No other architecture intentionally writes back dirty cache lines into
a buffer that a device has just finished writing into. If the cache is
clean, this has no effect at all, but if a cacheline in the buffer has
actually been written by the CPU,  there is a driver bug that is likely
made worse by overwriting that buffer.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20230816232336.164413-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 06c2afb8

arch/riscv/mm/dma-noncoherent.c

+1 −1
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, 
		break;

	case DMA_FROM_DEVICE:

	case DMA_BIDIRECTIONAL:

		ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);

		ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);

		break;

	default:

		break;