Commit eb4d8bac authored by Heiner Kallweit's avatar Heiner Kallweit Committed by Wolfram Sang
Browse files

i2c: i801: add helper i801_set_hstadd() 



Factor out setting SMBHSTADD to a helper. The current code makes the
assumption that constant I2C_SMBUS_READ has bit 0 set, that's not ideal.
Therefore let the new helper explicitly check for I2C_SMBUS_READ.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: default avatarJean Delvare <jdelvare@suse.de>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent e98a3bc0

drivers/i2c/busses/i2c-i801.c

+16 −20
Original line number Original line Diff line number Diff line
@@ -727,6 +727,11 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 
	return i801_check_post(priv, status);

	return i801_check_post(priv, status);

}

}





static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)

{

	outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));

}



/* Block transaction function */

/* Block transaction function */

static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,

static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,

				  char read_write, int command)

				  char read_write, int command)
@@ -797,28 +802,24 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, 




	switch (size) {

	switch (size) {

	case I2C_SMBUS_QUICK:

	case I2C_SMBUS_QUICK:

		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),

		i801_set_hstadd(priv, addr, read_write);

		       SMBHSTADD(priv));

		xact = I801_QUICK;

		xact = I801_QUICK;

		break;

		break;

	case I2C_SMBUS_BYTE:

	case I2C_SMBUS_BYTE:

		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),

		i801_set_hstadd(priv, addr, read_write);

		       SMBHSTADD(priv));

		if (read_write == I2C_SMBUS_WRITE)

		if (read_write == I2C_SMBUS_WRITE)

			outb_p(command, SMBHSTCMD(priv));

			outb_p(command, SMBHSTCMD(priv));

		xact = I801_BYTE;

		xact = I801_BYTE;

		break;

		break;

	case I2C_SMBUS_BYTE_DATA:

	case I2C_SMBUS_BYTE_DATA:

		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),

		i801_set_hstadd(priv, addr, read_write);

		       SMBHSTADD(priv));

		outb_p(command, SMBHSTCMD(priv));

		outb_p(command, SMBHSTCMD(priv));

		if (read_write == I2C_SMBUS_WRITE)

		if (read_write == I2C_SMBUS_WRITE)

			outb_p(data->byte, SMBHSTDAT0(priv));

			outb_p(data->byte, SMBHSTDAT0(priv));

		xact = I801_BYTE_DATA;

		xact = I801_BYTE_DATA;

		break;

		break;

	case I2C_SMBUS_WORD_DATA:

	case I2C_SMBUS_WORD_DATA:

		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),

		i801_set_hstadd(priv, addr, read_write);

		       SMBHSTADD(priv));

		outb_p(command, SMBHSTCMD(priv));

		outb_p(command, SMBHSTCMD(priv));

		if (read_write == I2C_SMBUS_WRITE) {

		if (read_write == I2C_SMBUS_WRITE) {

			outb_p(data->word & 0xff, SMBHSTDAT0(priv));

			outb_p(data->word & 0xff, SMBHSTDAT0(priv));
@@ -827,7 +828,7 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, 
		xact = I801_WORD_DATA;

		xact = I801_WORD_DATA;

		break;

		break;

	case I2C_SMBUS_PROC_CALL:

	case I2C_SMBUS_PROC_CALL:

		outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));

		i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);

		outb_p(command, SMBHSTCMD(priv));

		outb_p(command, SMBHSTCMD(priv));

		outb_p(data->word & 0xff, SMBHSTDAT0(priv));

		outb_p(data->word & 0xff, SMBHSTDAT0(priv));

		outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));

		outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
@@ -835,8 +836,7 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, 
		read_write = I2C_SMBUS_READ;

		read_write = I2C_SMBUS_READ;

		break;

		break;

	case I2C_SMBUS_BLOCK_DATA:

	case I2C_SMBUS_BLOCK_DATA:

		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),

		i801_set_hstadd(priv, addr, read_write);

		       SMBHSTADD(priv));

		outb_p(command, SMBHSTCMD(priv));

		outb_p(command, SMBHSTCMD(priv));

		block = 1;

		block = 1;

		break;

		break;
@@ -847,10 +847,9 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, 
		 * However if SPD Write Disable is set (Lynx Point and later),

		 * However if SPD Write Disable is set (Lynx Point and later),

		 * the read will fail if we don't set the R/#W bit.

		 * the read will fail if we don't set the R/#W bit.

		 */

		 */

		outb_p(((addr & 0x7f) << 1) |

		i801_set_hstadd(priv, addr,

		       ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?

				priv->original_hstcfg & SMBHSTCFG_SPD_WD ?

			(read_write & 0x01) : 0),

				read_write : I2C_SMBUS_WRITE);

		       SMBHSTADD(priv));

		if (read_write == I2C_SMBUS_READ) {

		if (read_write == I2C_SMBUS_READ) {

			/* NB: page 240 of ICH5 datasheet also shows

			/* NB: page 240 of ICH5 datasheet also shows

			 * that DATA1 is the cmd field when reading */

			 * that DATA1 is the cmd field when reading */
@@ -860,11 +859,8 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, 
		block = 1;

		block = 1;

		break;

		break;

	case I2C_SMBUS_BLOCK_PROC_CALL:

	case I2C_SMBUS_BLOCK_PROC_CALL:

		/*

		/* Needs to be flagged as write transaction */

		 * Bit 0 of the slave address register always indicate a write

		i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);

		 * command.

		 */

		outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));

		outb_p(command, SMBHSTCMD(priv));

		outb_p(command, SMBHSTCMD(priv));

		block = 1;

		block = 1;

		break;

		break;