Commit eb2feb68 authored by Thomas Richter's avatar Thomas Richter Committed by Arnaldo Carvalho de Melo
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perf vendor events s390: Remove UTF-8 characters from JSON file 



Commit 7f76b311 ("perf list: Add IBM z16 event description for
s390") contains the verbal description for z16 extended counter set.

However some entries of the public description contain UTF-8 characters
which breaks the build on some distros.

Fix this and remove the UTF-8 characters.

Fixes: 7f76b311 ("perf list: Add IBM z16 event description for s390")
Reported-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Suggested-by: default avatarHeiko Carstens <hca@linux.ibm.com>
Signed-off-by: default avatarThomas Richter <tmricht@linux.ibm.com>
Tested-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Cc: Sumanth Korikkar <sumanthk@linux.ibm.com>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Link: https://lore.kernel.org/r/ZBwkl77/I31AQk12@osiris


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6094c774

tools/perf/pmu-events/arch/s390/cf_z16/extended.json

+5 −5
Original line number Diff line number Diff line
@@ -95,28 +95,28 @@ 
		"EventCode": "145",

		"EventName": "DCW_REQ",

		"BriefDescription": "Directory Write Level 1 Data Cache from Cache",

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache."

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."

	},

	{

		"Unit": "CPU-M-CF",

		"EventCode": "146",

		"EventName": "DCW_REQ_IV",

		"BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention."

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."

	},

	{

		"Unit": "CPU-M-CF",

		"EventCode": "147",

		"EventName": "DCW_REQ_CHIP_HIT",

		"BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit",

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit."

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."

	},

	{

		"Unit": "CPU-M-CF",

		"EventCode": "148",

		"EventName": "DCW_REQ_DRAWER_HIT",

		"BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit",

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."

		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."

	},

	{

		"Unit": "CPU-M-CF",
@@ -284,7 +284,7 @@ 
		"EventCode": "172",

		"EventName": "ICW_REQ_DRAWER_HIT",

		"BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit",

		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."

		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."

	},

	{

		"Unit": "CPU-M-CF",